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GitHub / IlyaChichkov / RISC_V-CPU
Educational project which goal is realization of processor with RISC-V architecture.
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/IlyaChichkov%2FRISC_V-CPU
Stars: 0
Forks: 0
Open Issues: 0
License: None
Language: SystemVerilog
Repo Size: 282 KB
Dependencies:
0
Created: over 1 year ago
Updated: over 1 year ago
Last pushed: over 1 year ago
Last synced: about 1 year ago
Topics: hardware, risc-v, system-verilog
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No dependencies found