GitHub / edaa-org / pySVModel

An abstract language model of SystemVerilog (incl. Verilog) written in Python.

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/edaa-org%2FpySVModel
PURL: pkg:github/edaa-org/pySVModel

Stars: 9
Forks: 0
Open issues: 6

License: other
Language: Python
Size: 5.31 MB
Dependencies parsed at: Pending

Created at: almost 4 years ago
Updated at: 3 months ago
Pushed at: 19 days ago
Last synced at: 19 days ago

Topics: abstract, eda, edaa, model, python, system-verilog

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