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GitHub / edaa-org / pySVModel
An abstract language model of SystemVerilog (incl. Verilog) written in Python.
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/edaa-org%2FpySVModel
Stars: 7
Forks: 0
Open Issues: 1
License: other
Language: Python
Repo Size: 2.79 MB
Dependencies:
0
Created: over 2 years ago
Updated: 6 months ago
Last pushed: 4 months ago
Last synced: 4 days ago
Topics: abstract, eda, edaa, model, python, system-verilog
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