GitHub / michellavezzo / clock_verilog
First and Last Project for STRUCTURED DESIGN OF INTEGRATED CIRCUITS discipline at UFPB. 24h clock with system verilog + Functional verification.
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/michellavezzo%2Fclock_verilog
PURL: pkg:github/michellavezzo/clock_verilog
Stars: 0
Forks: 0
Open issues: 0
License: mit
Language: SystemVerilog
Size: 60.5 KB
Dependencies parsed at: Pending
Created at: almost 2 years ago
Updated at: over 1 year ago
Pushed at: over 1 year ago
Last synced at: over 1 year ago
Topics: 24h-clock, functional-verification, system-verilog, systemverilog, testbench, verilog