GitHub / RDSik / axis-spi

AXI-Stream SPI modules

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PURL: pkg:github/RDSik/axis-spi

Stars: 0
Forks: 0
Open issues: 2

License: mit
Language: SystemVerilog
Size: 56.6 KB
Dependencies parsed at: Pending

Created at: 4 months ago
Updated at: 3 months ago
Pushed at: 3 months ago
Last synced at: 3 months ago

Topics: fpga, make, modelsim, spi, systemverilog, tcl

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