RDSik/axis-modules

Some AXI-Stream modules

Language: SystemVerilog - Size: 388 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1 - Forks: 0

RDSik/FPGA-Awesome-list

List of useful materials on FPGA topic

Size: 265 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 4 - Forks: 0

RDSik/Zynq-Linux

Language: Tcl - Size: 5.12 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

RDSik/fir-filter

Language: SystemVerilog - Size: 0 Bytes - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

RDSik/axis-spi

AXI-Stream SPI modules

Language: SystemVerilog - Size: 56.6 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

RDSik/axis-i2c-master

AXI-Stream I2C Master module

Language: SystemVerilog - Size: 275 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 0

RDSik/FPGA-Tools-Docker

Docker Container with Iverilog, Yosys, Verilator, Verible, Gowin Education and more.

Language: Dockerfile - Size: 99.6 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 0

RDSik/tm1638-verilog Fork of alangarf/tm1638-verilog

A basic verilog driver for the TM1638 LED and key matrix chip

Language: SystemVerilog - Size: 1.38 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

RDSik/axis-fir-filter

Language: SystemVerilog - Size: 137 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

RDSik/verilog-transceiver

Educational project for the Xilinx ZedBoard Zynq-7000 Development Kit

Language: Verilog - Size: 636 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 3 - Forks: 0

RDSik/si5340-config-loader

Module for load configuration from ClockBuilderPro to Si5340 PLL via i2c interface

Language: Verilog - Size: 2.15 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 1 - Forks: 1

RDSik/digital-design-lab-manual

Мое решение задач из книги Цифровой синтез: практический курс

Language: Verilog - Size: 63.5 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

RDSik/schoolRISCV Fork of zhelnio/schoolRISCV

CPU microarchitecture, step by step

Language: Makefile - Size: 15.3 MB - Last synced at: 10 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0