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GitHub / maxdoublee / ADVANCED-VLSI-DESIGN---ECSE-6680
Max Destil's Advanced VLSI Design course project portfolio. See link for course description.
Stars: 0
Forks: 0
Open Issues: 0
License: None
Language: MATLAB
Repo Size: 28.2 MB
Dependencies:
0
Created: 2 months ago
Updated: about 1 month ago
Last pushed: about 1 month ago
Last synced: about 1 month ago
Topics: digital-signal-processing, filter-architectures, modelsim, parallel-processing, pipelining, quartus-prime, verilog
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