GitHub / VesalBargi / verilog-single-cycle-cpu
A ModelSim project that implements a MIPS single-cycle CPU using Verilog.
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Stars: 0
Forks: 0
Open issues: 0
License: mit
Language: Verilog
Size: 241 KB
Dependencies parsed at: Pending
Created at: 11 months ago
Updated at: 8 months ago
Pushed at: 8 months ago
Last synced at: 8 months ago
Topics: computer-architecture-lab, mips, modelsim, single-cycle-processor, verilog
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