GitHub / Nishit-2006 / RISC-V-RV32I-Pipelined-Processor-Verilog-Implementation-
Implement a 5-stage pipelined RISC-V RV32I processor in Verilog. Includes a custom Python assembler for easy instruction translation. 🖥️🚀
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PURL: pkg:github/Nishit-2006/RISC-V-RV32I-Pipelined-Processor-Verilog-Implementation-
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License: None
Language: Verilog
Size: 40.7 MB
Dependencies parsed at: Pending
Created at: 9 days ago
Updated at: 9 days ago
Pushed at: 7 days ago
Last synced at: 7 days ago
Topics: architecture, hardware-designs, instruction-set-architecture, microprocessor, modelsim, pipelining, processor, riscv, riscv32, rv32i, systemverilog, systemverilog-hdl, verilog