An open API service providing repository metadata for many open source software ecosystems.

GitHub topics: sdram-controller

ultraembedded/core_sdram_axi4

SDRAM controller with AXI4 interface

Language: C++ - Size: 43 KB - Last synced at: 2 months ago - Pushed at: almost 6 years ago - Stars: 92 - Forks: 31

yasnakateb/SdramController

🛠 A SDRAM controller in Verilog HDL

Language: Verilog - Size: 47.9 KB - Last synced at: 4 months ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

teekamkhandelwal/SRAM_Controller

The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.

Language: Verilog - Size: 72.3 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 1 - Forks: 0

cw1997/SDRAM-Controller

SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

Language: HTML - Size: 1.5 MB - Last synced at: 3 months ago - Pushed at: about 3 years ago - Stars: 10 - Forks: 2

oskarwires/sdram_controller

High-Speed SystemVerilog SDRAM Controller

Language: SystemVerilog - Size: 151 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

yigitbektasgursoy/SDRAM_Verilog

Verilog HDL implementation of SDRAM controller and SDRAM model

Language: Verilog - Size: 781 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

Edwyrion/sdram-controller

Basic implementation of SDRAM controller for De0-nano board.

Language: Verilog - Size: 15.6 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

PrimeMHD/FPGA_ThreeLevelStorage

【原创,已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计,FPGA三级存储子系统。

Language: Coq - Size: 40.1 MB - Last synced at: about 1 year ago - Pushed at: almost 5 years ago - Stars: 107 - Forks: 26

agg23/sdram-controller

A HDL SDRAM controller designed for retro hardware and FPGAs

Language: SystemVerilog - Size: 61.5 KB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 3

Arkowski24/sdram-controller

Simple SDRAM Controller for DE10-Lite.

Language: Verilog - Size: 71.3 KB - Last synced at: about 1 year ago - Pushed at: over 6 years ago - Stars: 9 - Forks: 3

armleo/sdram_controller

SDR SDRAM Controller with Avalon-MM bus;

Language: Verilog - Size: 1.36 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 1

AngeloJacobo/FPGA_SDRAM_Controller

SDRAM controller optimized to a memory bandwidth of 316MB/s

Language: Verilog - Size: 18.6 KB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 13 - Forks: 1

egk696/EDAC_SDRAM_Controller

Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller

Language: Verilog - Size: 94.4 MB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 8 - Forks: 2

jakubcabal/sdram-tester-fpga

SDRAM Tester implemented in FPGA

Language: VHDL - Size: 60.5 KB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 7 - Forks: 1

MinatsuT/CYC1000_SDRAM

A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)

Language: Verilog - Size: 554 KB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 9 - Forks: 0