GitHub topics: memory-controller
krzk/linux Fork of torvalds/linux
This is not Linux kernel maintainer's tree, but an open-source work in progress. Officially maintained repositories are under kernel.org (Samsung SoC, memory controller drivers etc.).
Language: C - Size: 5.48 GB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 12 - Forks: 2
AngeloJacobo/UberDDR3
Opensource DDR3 Controller
Language: Verilog - Size: 64.6 MB - Last synced at: 18 days ago - Pushed at: 18 days ago - Stars: 340 - Forks: 47
FlorianFrank/verilog_baremetal_sram_controller
A bare-metal SRAM memory controller suitable for Xilinx FPGAs.
Language: Verilog - Size: 775 KB - Last synced at: 5 days ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 0
someone755/ddr3-controller
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
Language: Verilog - Size: 215 KB - Last synced at: 16 days ago - Pushed at: over 2 years ago - Stars: 71 - Forks: 11
szym-mie/vga3
Redesign of 'vga_src' video card architcture using proper FIFOs
Language: Verilog - Size: 3.56 MB - Last synced at: 26 days ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
yasnakateb/SdramController
🛠A SDRAM controller in Verilog HDL
Language: Verilog - Size: 47.9 KB - Last synced at: 4 months ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0
Elphel/eddr3
mirror of https://git.elphel.com/Elphel/eddr3
Language: Verilog - Size: 1.49 MB - Last synced at: 7 months ago - Pushed at: over 7 years ago - Stars: 39 - Forks: 17
teekamkhandelwal/SRAM_Controller
The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.
Language: Verilog - Size: 72.3 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 1 - Forks: 0
