GitHub topics: 32-bit-fast-adder
Vedant-02/Verilog-HDL-Lab-Experiments
Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur
Language: Verilog - Size: 102 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 2
Related Keywords
32-bit-alu
1
32-bit-fast-adder
1
4-bit-combinational-adder
1
4-bit-comparator
1
4-bit-parallel-adder
1
adder-subtractor
1
barrel-shifter
1
bcd-adder
1
bcd-subtractor
1
bcd-to-7-segment
1
binary-multiplier
1
binary-to-gray
1
carry-look-ahead-adder
1
carry-select-adder
1
carry-skip-adder
1
full-adder
1
hacktoberfest
1
hacktoberfest2022
1
priority-encoder
1
verilog
1