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GitHub / adityagupta1089 / EEP206-Verilog

Verilog Codes for various digital circuits for labs at IIT Ropar, basic gates, adders & subtractors (half & full), ripple adders, multipliers and code converters.

JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/adityagupta1089%2FEEP206-Verilog

Stars: 3
Forks: 2
Open Issues: 0

License: None
Language: Verilog
Repo Size: 18.6 KB
Dependencies: 0

Created: over 7 years ago
Updated: about 1 year ago
Last pushed: about 7 years ago
Last synced: 10 months ago

Topics: adder, bcd, digital-circuits, gates, multipliers, ripple-adders, subtractor, verilog

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