GitHub / Abdelrahman1810 / SPI_Slave_with_Single_Port_RAM

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Abdelrahman1810%2FSPI_Slave_with_Single_Port_RAM

Topics: finite-state-machine, questasim, rtl, rtl-design, synthesis, systemverilog, testbench, verilog, vivado

Files

No dependencies found