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GitHub topics: edge-detector-with-mealy

snbk001/100DaysofRTL

100DaysofRTL: basic logic gates, mux, half and full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector with Moore, Edge Detector with Mealy

Language: SystemVerilog - Size: 120 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 7 - Forks: 2

Related Keywords
edge-detector-with-mealy 1 hdl 1 makefile 1 rtl-design 1 synthesis 1 systemverilog 1 systemverilog-hdl 1 systemverilog-simulation 1 systemverilog-test-bench 1 testbench 1 verilog 1