GitHub / TahirZia-1 / RISC-V-CPU-Core-SystemVerilog

This repository contains a SystemVerilog implementation of a basic 5-stage pipeline RISC-V processor. The processor includes a register file, ALU, control unit, instruction memory, and data memory. It is designed to run simple assembly programs and includes optimizations for performance such as hazard detection, forwarding, and branch prediction.

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Topics: alu, assembly-language, cpu, fpga, fpga-programming, processor, registers, risc-v, riscv, riscvprocessor, simulation, systemverilog, verilog, vivado

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