GitHub / yuanbo-peng / Combination-Lock
This project is to implement a combination lock on the FPGA board using VHDL language and finite state machine. There are some possible solutions are provided to address the problems including debounce, random number generation and combination check.
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/yuanbo-peng%2FCombination-Lock
PURL: pkg:github/yuanbo-peng/Combination-Lock
Stars: 8
Forks: 3
Open issues: 0
License: None
Language: VHDL
Size: 1020 KB
Dependencies parsed at: Pending
Created at: over 5 years ago
Updated at: 5 months ago
Pushed at: about 5 years ago
Last synced at: 2 months ago
Topics: combination-lock, debounce-button, digital-design, finite-state-machine, multi-digits-display, nexys4, random-numbers, vhdl, vivado