GitHub / arunbasilpaul 1 Repository
Building Embedded systems to creatively help people. Passionate for safety-critical systems with a specialization in FPGA(s) and Machine Learning.
arunbasilpaul/FIFO-Synchronous-vs-Asynchronous
This project explores the simplicity / complexity of a synchronous and asynchronous FIFO. FIFO is a valuable component during data transmission, in particular during clock-domain crossing for multi-bit data. Therefore, we dive it into designing a synchronous and asynchronous FIFO to compare their similarities and differences.
Language: VHDL - Size: 6.84 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0
arunbasilpaul/Alarm_Clock
A HDL twist to the traditional Alarm Clock with opportunity to set an alarm and a 7-segment display
Language: VHDL - Size: 61.5 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0
arunbasilpaul/arunbasilpaul
Size: 73.2 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0
arunbasilpaul/Custom-Pynq-OS-development-with-Petalinux
Size: 62.5 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0