GitHub / arunbasilpaul / FIFO-Synchronous-vs-Asynchronous
This project explores the simplicity / complexity of a synchronous and asynchronous FIFO. FIFO is a valuable component during data transmission, in particular during clock-domain crossing for multi-bit data. Therefore, we dive it into designing a synchronous and asynchronous FIFO to compare their similarities and differences.
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License: None
Language: VHDL
Size: 6.84 KB
Dependencies parsed at: Pending
Created at: about 1 month ago
Updated at: about 1 month ago
Pushed at: about 1 month ago
Last synced at: about 1 month ago
Topics: asynchronous, cross-clock-domain, synchronous, vhdl