GitHub / NajimAlfutini / Design-A-Full-SRC-Processor
The project involves designing a Simple RISC Computer (SRC) processor with 23 instructions, 32 registers, a control unit, data path, and memory components, aiming to create a functional CPU architecture capable of executing instructions.
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PURL: pkg:github/NajimAlfutini/Design-A-Full-SRC-Processor
Stars: 0
Forks: 0
Open issues: 0
License: mit
Language: HTML
Size: 4.5 MB
Dependencies parsed at: Pending
Created at: over 1 year ago
Updated at: over 1 year ago
Pushed at: over 1 year ago
Last synced at: over 1 year ago
Topics: alu, control-unit, cpu, isa, memory, pipeline