GitHub / RSPwFPGAs / virtio-fpga-bridge

Virtio front-end and back-end bridge, implemented with FPGA.

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/RSPwFPGAs%2Fvirtio-fpga-bridge
PURL: pkg:github/RSPwFPGAs/virtio-fpga-bridge

Stars: 20
Forks: 7
Open issues: 0

License: bsd-3-clause
Language: SystemVerilog
Size: 3.94 MB
Dependencies parsed at: Pending

Created at: about 5 years ago
Updated at: over 1 year ago
Pushed at: almost 5 years ago
Last synced at: over 1 year ago

Topics: cosim, fpga, pcie, qemu, virtio

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