GitHub / Scrawach / riscv
Pipelined CPU microarchitecture RISC-V ISA RV32I.
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PURL: pkg:github/Scrawach/riscv
Stars: 1
Forks: 1
Open issues: 0
License: None
Language: Verilog
Size: 1.15 MB
Dependencies parsed at: Pending
Created at: over 3 years ago
Updated at: over 2 years ago
Pushed at: about 3 years ago
Last synced at: over 2 years ago
Topics: cpu, microarchitecture, risc-v, riscv, rtl, rv32i
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