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GitHub / ShashankVM / generic_systemverilog_designs_library

A library of useful, fully parameterized RTL designs implemented in SystemVerilog.

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ShashankVM%2Fgeneric_systemverilog_designs_library

Stars: 3
Forks: 1
Open issues: 0

License: bsd-3-clause
Language: SystemVerilog
Size: 39.1 KB
Dependencies parsed at: Pending

Created at: over 4 years ago
Updated at: almost 3 years ago
Pushed at: about 3 years ago
Last synced at: about 2 years ago

Topics: basic-learning, digital-logic-design, systemverilog

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