GitHub / Yellowflash-070 / BIST-for-6bit-CLA
A Built in Self Test (BIST) controller is created in Verilog HDL to test a 6-bit Carry Lookahead Adder (CLA) utilising a 4-bit Signature Output Response Analyser (ORA).
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Yellowflash-070%2FBIST-for-6bit-CLA
PURL: pkg:github/Yellowflash-070/BIST-for-6bit-CLA
Stars: 0
Forks: 0
Open issues: 0
License: gpl-3.0
Language: Verilog
Size: 25.4 KB
Dependencies parsed at: Pending
Created at: about 1 year ago
Updated at: about 1 year ago
Pushed at: about 1 year ago
Last synced at: about 1 year ago
Topics: 4bitsignature, 6bitcla, bist, carry-look-ahead-adder, lfsr, ora, testing, verilog