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GitHub / chipsalliance / UHDM
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2FUHDM
Stars: 181
Forks: 37
Open issues: 14
License: apache-2.0
Language: C++
Size: 4.36 MB
Dependencies parsed at:
4
Created at: over 4 years ago
Updated at: 28 days ago
Pushed at: 28 days ago
Last synced at: 28 days ago
Topics: ieee-standard, listener, serialization, systemverilog, vpi-api, vpi-interface
Files
Dependencies
- actions/checkout v3 composite
- actions/setup-python v4 composite
- hendrikmuhs/ccache-action v1.2 composite
- msys2/setup-msys2 v2 composite