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GitHub / egk696 / InterChip_Bridge
A Fault Tolerant Globally-Asynchronous-Locally-Synchronous Inter-Chip Communication Bridge on FPGAs
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/egk696%2FInterChip_Bridge
Stars: 4
Forks: 2
Open Issues: 0
License: mit
Language: VHDL
Repo Size: 14.6 KB
Dependencies: pending
Created: over 6 years ago
Updated: 8 months ago
Last pushed: over 6 years ago
Last synced: 4 months ago
Commit Stats
Commits: 2
Authors: 1
Mean commits per author: 2.0
Development Distribution Score: 0.0
More commit stats: https://commits.ecosyste.ms/hosts/GitHub/repositories/egk696/InterChip_Bridge
Topics: asynchronous, clock-domain-crossing, communication-protocol, embedded-systems, fault-detection, fault-tolerant, fpga, interchip-bridge, network-on-chip