GitHub / ivanMilin / RISCV_multicore_cache_controller
This project is a final project in my master studies and it's done in a team of 2 people, Petar Stamenkovic and myself.
Stars: 4
Forks: 1
Open issues: 0
License: None
Language: SystemVerilog
Size: 14.8 MB
Dependencies parsed at: Pending
Created at: 8 months ago
Updated at: about 2 months ago
Pushed at: 4 months ago
Last synced at: 18 days ago
Commit Stats
Commits: 46
Authors: 3
Mean commits per author: 15.33
Development Distribution Score: 0.543
More commit stats: https://commits.ecosyste.ms/hosts/GitHub/repositories/ivanMilin/RISCV_multicore_cache_controller
Topics: assembly, formal-verification, jasper-gold, multicore-cpu, ripes, risc-v, singlecycle-processor, systemverilog