GitHub / jpsety / verilog_benchmark_circuits
EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
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Stars: 7
Forks: 2
Open issues: 0
License: None
Language: Verilog
Size: 4.56 MB
Dependencies parsed at: Pending
Created at: over 5 years ago
Updated at: about 2 years ago
Pushed at: over 5 years ago
Last synced at: about 2 years ago
Topics: benchmark, circuits, epfl, iscas, verilog
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