GitHub / kropotin4 / SystemVerilog-examples
Попытка написать несколько примеров кода на языке SystemVerilog.
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Stars: 1
Forks: 0
Open issues: 0
License: None
Language: SystemVerilog
Size: 25.4 KB
Dependencies parsed at: Pending
Created at: about 4 years ago
Updated at: about 4 years ago
Pushed at: about 4 years ago
Last synced at: about 2 years ago
Topics: questasim, rtl, systemverilog
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