GitHub / nelsoncsc / basic_uvmc
A simple testbench with two refmods using UVM Connect
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Stars: 2
Forks: 2
Open issues: 0
License: mit
Language: SystemVerilog
Size: 9.77 KB
Dependencies parsed at: Pending
Created at: over 8 years ago
Updated at: about 2 years ago
Pushed at: over 7 years ago
Last synced at: about 2 years ago
Topics: functional-verification, systemc, systemverilog-hdl, uvm
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