GitHub / rpigor / TPSim

TPSim (Timing and Power Simulator) is a gate-level circuit simulator with timing and power estimation capabilities

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rpigor%2FTPSim
PURL: pkg:github/rpigor/TPSim

Stars: 0
Forks: 0
Open issues: 0

License: mit
Language: C++
Size: 134 KB
Dependencies parsed at: Pending

Created at: about 1 year ago
Updated at: 3 months ago
Pushed at: 3 months ago
Last synced at: about 1 month ago

Topics: eda, power-analysis, simulator, timing-analysis, verilog

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