GitHub topics: cse14-iiith
virtual-labs/exp-layout-design-iiith
This experiment belongs to VLSI Lab IIITH. Name: Layout Design
Language: HTML - Size: 2.34 MB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
virtual-labs/exp-spice-code-platform-iiith
This experiment belongs to VLSI Lab IIITH. Name: Spice Code Platform
Language: HTML - Size: 3.79 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
virtual-labs/exp-d-flip-flop-verilog-iiith
This experiment belongs to VLSI Lab IIITH. Name: Design Of D-Flip Flop Using Verilog
Language: Java - Size: 15.9 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
virtual-labs/exp-digital-circuits-verilog-iiith
This experiment belongs to VLSI Lab IIITH. Name: Design Of Digital Circuits Using Verilog
Language: JavaScript - Size: 15.4 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
virtual-labs/exp-pass-transistor-logic-iiith
This experiment belongs to VLSI Lab IIITH. Name: Schematic Design Of Pass Transistor Logic & Multiplexer
Language: JavaScript - Size: 3.17 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0
virtual-labs/exp-chain-of-inverters-iiith
This experiment belongs to VLSI Lab IIITH. Name: Delay Estimation In Chain Of Inverters
Language: JavaScript - Size: 2.06 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
virtual-labs/exp-transistor-level-inverter-iiith
This experiment belongs to VLSI Lab IIITH. Name: Schematic Design Of Transistor Level Inverter
Language: JavaScript - Size: 2.14 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 1
virtual-labs/exp-transistor-level-xor-iiith
This experiment belongs to VLSI Lab IIITH. Name: Schematic Design Of Transistor Level XOR & XNOR Gate
Language: JavaScript - Size: 2.35 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0
virtual-labs/exp-transistor-level-nand-iiith
This experiment belongs to VLSI Lab IIITH. Name: Schematic Design Of Transistor Level NAND & NOR Gate
Language: JavaScript - Size: 2.26 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0
virtual-labs/exp-d-latch-and-d-flip-flop-iiith
This experiment belongs to VLSI Lab IIITH. Name: Schematic Design Of D-Latch and D-Flip Flop
Language: JavaScript - Size: 3.9 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0
virtual-labs-archive/vlsi-iiith-js
This repository contains sources for VLSI lab
Language: Java - Size: 47.6 MB - Last synced at: 9 months ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 5
