GitHub topics: reproducible-computation
stillwater-sc/RISC-V-TensorCore
Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
Language: Verilog - Size: 143 KB - Last synced at: 9 months ago - Pushed at: over 3 years ago - Stars: 44 - Forks: 14
wlandau/larug2020
Presentation about the targets R package at the Los Angeles R Users Group Meetup
Language: HTML - Size: 2.33 MB - Last synced at: 25 days ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 1
