GitHub topics: t13x
klessydra/T03x
A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores
Language: VHDL - Size: 1.03 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 13 - Forks: 2
klessydra/T13x
An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP
Language: VHDL - Size: 6.96 MB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 39 - Forks: 11
klessydra/T02x
A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores
Language: VHDL - Size: 1.04 MB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 17 - Forks: 4