Ecosyste.ms: Repos
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GitLab.com topics: Xilinx
xlogic/systemd/flexlm
Using containerized FlexLM license managers as systemd service units for serving FPGA/ASIC EDA software licenses that can be also used in CI/CD flow.
Last synced: 5 months ago - Stars: 1 - Forks: 0
![](https://gitlab.com/uploads/-/system/project/avatar/47026802/license-manager.png)
_solis/embedded_systems
All VHDL code used for Embedded Systems Lab
Last synced: over 1 year ago - Stars: 0 - Forks: 0
sbannier/machet
A collection of Perl scripts for digital design simulation and FPGA synthesis automation. It supports Verilog, VHDL and mixed language (Verilog + VHDL) designs.
Last synced: over 1 year ago - Stars: 0 - Forks: 0
rodrigomelo9/pyfpga
A Python package to use FPGA development tools programmatically. It is a mirror of https://github.com/PyFPGA/pyfpga, where the development is done. Documentation: https://pyfpga.github.io/pyfpga
Last synced: over 1 year ago - Stars: 10 - Forks: 1
![](https://gitlab.com/uploads/-/system/project/avatar/14953398/logo.png)
busshark/thirdparty/libxsvf
a fork of http://svn.clifford.at/libxsvf/trunk@104
Last synced: over 1 year ago - Stars: 1 - Forks: 1
acj0003/zynq_coresight
An Demonstration of FPGA Assisted Software Tracing for ARM CoreSight On Xilinx Zynq-7000 SoC
Last synced: over 1 year ago - Stars: 0 - Forks: 0
tymonx/logic-toolchain
Wrapper for FPGA toolchain tools
Last synced: 29 days ago - Stars: 0 - Forks: 0
fvb/MIPS_processor
MIPS processor implementation in VHDL which was the project for the computer architecture class at VUB
Last synced: over 1 year ago - Stars: 1 - Forks: 0