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Topic: "electronics-design-automation"

NYU-MLDA/OpenABC

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

Language: Verilog - Size: 26.8 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 103 - Forks: 19

Gy-Hu/EDA_FV_conference_deadline

Countdown for EDA and formal verification conference deadlines

Language: HTML - Size: 121 KB - Last synced at: 3 days ago - Pushed at: 11 months ago - Stars: 4 - Forks: 0

NYU-MLDA/ALMOST

ALMOST: Adversarial Learning to Mitigate Oracle-less ML Logic Locking Attacks via Synthesis Tuning

Language: Verilog - Size: 74.1 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 2 - Forks: 0

animeshbchowdhury/RTL_dataset

Extract leaf level RTL modules from OpenROAD and collect PPA numbers generated by Yosys

Language: Verilog - Size: 6.92 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Related Topics
logic-synthesis 3 electronics-design 2 graph-machine-learning 2 graph-neural-networks 2 openabc-d 1 logic-synthesis-benchmarks 1 deep-learning 1 datasets 1 circuit-benchmarks 1 bulls-eye 1 boolean-optimization 1 benchmarks 1 formal-verification 1 conference-deadlines 1 simulated-annealing 1 machine-learning-attack 1 logic-locking 1 adversarial-learning 1 adversarial-attacks 1 labeled-data 1