Topic: "isa-architecture"
justin-marian/tiny-risc-v
Minimalist RISC-V with a five-stage pipeline. It serves as a platform for understanding processor design principles.
Language: Verilog - Size: 28.4 MB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
yttty/exp-isa 📦
An experimental Instruction Set Architecture (ISA) and the implementation of a CPU simulator and an assembler.
Language: C - Size: 49.8 KB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 0 - Forks: 1
