Topic: "verilog"
logisim-evolution/logisim-evolution
Digital logic design tool and simulator
Language: Java - Size: 110 MB - Last synced at: about 2 hours ago - Pushed at: about 4 hours ago - Stars: 6,475 - Forks: 819
chipsalliance/chisel
Chisel: A Modern Hardware Design Language
Language: Scala - Size: 160 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 4,469 - Forks: 640
open-sdr/openwifi
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
Language: C - Size: 24.5 MB - Last synced at: about 22 hours ago - Pushed at: about 23 hours ago - Stars: 4,411 - Forks: 738
LeiWang1999/FPGA
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
Size: 58.6 KB - Last synced at: about 1 year ago - Pushed at: over 3 years ago - Stars: 3,905 - Forks: 658
verilator/verilator
Verilator open-source SystemVerilog simulator and lint system
Language: C++ - Size: 64.3 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 3,168 - Forks: 715
SpinalHDL/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
Language: Assembly - Size: 12.7 MB - Last synced at: 6 months ago - Pushed at: 7 months ago - Stars: 2,775 - Forks: 446
SI-RISCV/e200_opensource 📦
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
Language: Verilog - Size: 90.1 MB - Last synced at: 6 months ago - Pushed at: over 4 years ago - Stars: 2,720 - Forks: 1,036
darklife/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Language: Verilog - Size: 3.99 MB - Last synced at: 3 months ago - Pushed at: 4 months ago - Stars: 2,386 - Forks: 314
The-OpenROAD-Project/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Language: Verilog - Size: 837 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 2,267 - Forks: 730
cocotb/cocotb
cocotb: Python-based chip (RTL) verification
Language: Python - Size: 9.96 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 2,142 - Forks: 594
jbush001/NyuziProcessor
GPGPU microprocessor architecture
Language: C - Size: 31.4 MB - Last synced at: 6 months ago - Pushed at: about 1 year ago - Stars: 2,082 - Forks: 360
SpinalHDL/SpinalHDL
Scala based HDL
Language: Scala - Size: 98.7 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 1,874 - Forks: 362
pConst/basic_verilog
Must-have verilog systemverilog modules
Language: Verilog - Size: 54.2 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1,815 - Forks: 408
FPGAwars/icestudio
:snowflake: Visual editor for open FPGA boards
Language: JavaScript - Size: 120 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1,803 - Forks: 260
analogdevicesinc/hdl
HDL libraries and projects
Language: Verilog - Size: 106 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 1,774 - Forks: 1,608
olofk/serv
SERV - The SErial RISC-V CPU
Language: Verilog - Size: 12.5 MB - Last synced at: 21 days ago - Pushed at: about 1 month ago - Stars: 1,661 - Forks: 231
The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Language: Python - Size: 836 MB - Last synced at: about 1 month ago - Pushed at: 2 months ago - Stars: 1,597 - Forks: 403
clash-lang/clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
Language: Haskell - Size: 20 MB - Last synced at: about 13 hours ago - Pushed at: about 15 hours ago - Stars: 1,554 - Forks: 164
riscv-mcu/e203_hbirdv2
The Ultra-Low Power RISC-V Core
Language: Verilog - Size: 59.5 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1,552 - Forks: 382
ZipCPU/zipcpu
A small, light weight, RISC CPU soft core
Language: Verilog - Size: 256 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1,442 - Forks: 171
ultraembedded/riscv
RISC-V CPU Core (RV32IM)
Language: Verilog - Size: 5.27 MB - Last synced at: 8 months ago - Pushed at: about 4 years ago - Stars: 1,398 - Forks: 251
google/xls
XLS: Accelerated HW Synthesis
Language: C++ - Size: 71.5 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1,369 - Forks: 217
olofk/fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
Language: Python - Size: 2.38 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1,360 - Forks: 263
platformio/platformio-vscode-ide
PlatformIO IDE for VSCode: The next generation integrated development environment for IoT
Language: JavaScript - Size: 1.96 MB - Last synced at: about 2 months ago - Pushed at: 10 months ago - Stars: 1,326 - Forks: 219
chili-chips-ba/wireguard-fpga
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
Language: Verilog - Size: 1.98 GB - Last synced at: about 8 hours ago - Pushed at: about 10 hours ago - Stars: 1,259 - Forks: 29
verilog-to-routing/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Language: C++ - Size: 351 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1,163 - Forks: 430
aappleby/metroboy
A repository of gate-level simulators and tools for the original Game Boy.
Language: C++ - Size: 72.8 MB - Last synced at: 6 months ago - Pushed at: 9 months ago - Stars: 1,139 - Forks: 36
siliconcompiler/siliconcompiler
Modular hardware build system
Language: Python - Size: 342 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 1,104 - Forks: 113
drom/awesome-hdl
Hardware Description Languages
Size: 171 KB - Last synced at: 8 days ago - Pushed at: 4 months ago - Stars: 1,072 - Forks: 101
ultraembedded/biriscv
32-bit Superscalar RISC-V CPU
Language: Verilog - Size: 2.98 MB - Last synced at: 6 months ago - Pushed at: about 4 years ago - Stars: 1,021 - Forks: 171
splinedrive/kianRiscV
RISC-V XV6/Linux SoC, marchID: 0x2b
Language: Verilog - Size: 200 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 983 - Forks: 68
circuitvalley/USB_C_Industrial_Camera_FPGA_USB3
Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
Language: Verilog - Size: 57.4 MB - Last synced at: 6 months ago - Pushed at: about 2 years ago - Stars: 969 - Forks: 186
hughperkins/VeriGPU
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
Language: SystemVerilog - Size: 6.76 MB - Last synced at: 8 months ago - Pushed at: 12 months ago - Stars: 961 - Forks: 109
FPGAwars/apio
:seedling: Open source ecosystem for open FPGA boards
Language: Python - Size: 149 MB - Last synced at: 18 days ago - Pushed at: 18 days ago - Stars: 905 - Forks: 152
syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Language: SystemVerilog - Size: 5.49 MB - Last synced at: 8 months ago - Pushed at: about 1 year ago - Stars: 904 - Forks: 284
MikePopoloski/slang
SystemVerilog compiler and language services
Language: C++ - Size: 32.1 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 875 - Forks: 182
veryl-lang/veryl
Veryl: A Modern Hardware Description Language
Language: Rust - Size: 81.3 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 827 - Forks: 49
Obijuan/open-fpga-verilog-tutorial
Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
Language: Verilog - Size: 36.6 MB - Last synced at: 6 months ago - Pushed at: over 5 years ago - Stars: 804 - Forks: 199
lvyufeng/step_into_mips
一步一步写MIPS CPU
Language: Verilog - Size: 34.2 MB - Last synced at: 8 months ago - Pushed at: over 4 years ago - Stars: 785 - Forks: 157
Redcrafter/verilog2factorio
This project will compile verilog (a hardware description language) into factorio blueprints.
Language: TypeScript - Size: 6.65 MB - Last synced at: 6 months ago - Pushed at: 10 months ago - Stars: 781 - Forks: 22
open-sdr/openwifi-hw
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
Language: Verilog - Size: 484 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 778 - Forks: 268
nickg/nvc
VHDL compiler and simulator
Language: C - Size: 27.1 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 754 - Forks: 96
ultraembedded/cores
Various HDL (Verilog) IP Cores
Language: Verilog - Size: 211 KB - Last synced at: 9 months ago - Pushed at: over 4 years ago - Stars: 745 - Forks: 218
PrincetonUniversity/openpiton
The OpenPiton Platform
Language: Assembly - Size: 88.7 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 730 - Forks: 249
WangXuan95/FPGA-USB-Device
An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed) device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。
Language: Verilog - Size: 494 KB - Last synced at: 7 months ago - Pushed at: 12 months ago - Stars: 722 - Forks: 120
olofk/edalize
An abstraction library for interfacing EDA tools
Language: Python - Size: 1.08 MB - Last synced at: 21 days ago - Pushed at: about 1 month ago - Stars: 718 - Forks: 218
WangXuan95/FPGA-FOC
An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
Language: Verilog - Size: 666 KB - Last synced at: 5 months ago - Pushed at: about 2 years ago - Stars: 700 - Forks: 208
rejunity/z80-open-silicon
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
Language: Verilog - Size: 90.4 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 697 - Forks: 28
zachjs/sv2v
SystemVerilog to Verilog conversion
Language: Haskell - Size: 1.94 MB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 670 - Forks: 60
TerosTechnology/vscode-terosHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Language: VHDL - Size: 152 MB - Last synced at: 28 days ago - Pushed at: about 2 months ago - Stars: 654 - Forks: 57
projf/projf-explore
Project F brings FPGAs to life with exciting open-source designs you can build on.
Language: SystemVerilog - Size: 3.05 MB - Last synced at: 7 months ago - Pushed at: 10 months ago - Stars: 637 - Forks: 56
OpenTimer/OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
Language: Verilog - Size: 329 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 633 - Forks: 159
xiaop1/Verilog-Practice
HDLBits website practices & solutions
Language: Verilog - Size: 68.4 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 592 - Forks: 164
WangXuan95/BSV_Tutorial_cn
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
Language: Bluespec - Size: 31.1 MB - Last synced at: 7 months ago - Pushed at: about 2 years ago - Stars: 566 - Forks: 44
ben-marshall/awesome-open-hardware-verification
A List of Free and Open Source Hardware Verification Tools and Frameworks
Size: 166 KB - Last synced at: 8 days ago - Pushed at: about 2 years ago - Stars: 564 - Forks: 54
seldridge/verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
Language: Verilog - Size: 72.3 KB - Last synced at: 8 months ago - Pushed at: over 7 years ago - Stars: 564 - Forks: 140
openrisc/mor1kx
mor1kx - an OpenRISC 1000 processor IP core
Language: Verilog - Size: 2.78 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 550 - Forks: 151
dalance/svls
SystemVerilog language server
Language: Rust - Size: 868 KB - Last synced at: 21 days ago - Pushed at: about 1 month ago - Stars: 543 - Forks: 31
The-OpenROAD-Project/OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Language: Verilog - Size: 841 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 515 - Forks: 395
platformio/platformio-atom-ide 📦
PlatformIO IDE for Atom: The next generation integrated development environment for IoT
Language: JavaScript - Size: 1.12 MB - Last synced at: 3 months ago - Pushed at: about 5 years ago - Stars: 475 - Forks: 71
jofrfu/tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Language: VHDL - Size: 1.42 MB - Last synced at: 6 months ago - Pushed at: almost 7 years ago - Stars: 465 - Forks: 66
fabriziotappero/ip-cores
A huge collection of VHDL/Verilog open-source IP cores scraped from the web
Size: 649 MB - Last synced at: 7 months ago - Pushed at: almost 3 years ago - Stars: 459 - Forks: 138
dalance/sv-parser
SystemVerilog parser library fully compliant with IEEE 1800-2017
Language: Rust - Size: 48.2 MB - Last synced at: 20 days ago - Pushed at: 9 months ago - Stars: 452 - Forks: 61
jks-prv/Beagle_SDR_GPS
KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS
Language: C++ - Size: 269 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 452 - Forks: 155
vmware-archive/cascade 📦
A Just-In-Time Compiler for Verilog from VMware Research
Language: C++ - Size: 19.2 MB - Last synced at: 15 days ago - Pushed at: over 4 years ago - Stars: 447 - Forks: 44
hunterlew/convolution_network_on_FPGA
CNN acceleration on virtex-7 FPGA with verilog HDL
Language: Verilog - Size: 1.64 MB - Last synced at: 5 months ago - Pushed at: over 7 years ago - Stars: 447 - Forks: 138
tommythorn/Reduceron
FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.
Language: Haskell - Size: 8.86 MB - Last synced at: about 1 month ago - Pushed at: 4 months ago - Stars: 446 - Forks: 34
T-K-233/RISC-V-Single-Cycle-CPU
RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel
Language: Verilog - Size: 16.7 MB - Last synced at: 8 months ago - Pushed at: 10 months ago - Stars: 433 - Forks: 45
pymtl/pymtl3
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
Language: Python - Size: 5.39 MB - Last synced at: 21 days ago - Pushed at: 3 months ago - Stars: 431 - Forks: 57
rggen/rggen
Code generation tool for control and status registers
Language: Ruby - Size: 594 KB - Last synced at: 28 days ago - Pushed at: 2 months ago - Stars: 427 - Forks: 55
chipsalliance/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
Language: C++ - Size: 855 MB - Last synced at: 28 days ago - Pushed at: 2 months ago - Stars: 422 - Forks: 77
abdelazeem201/ASIC-Design-Roadmap
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.
Language: Verilog - Size: 5.77 MB - Last synced at: 6 days ago - Pushed at: 4 months ago - Stars: 418 - Forks: 56
jhshi/openofdm
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
Language: Verilog - Size: 26.8 MB - Last synced at: 8 months ago - Pushed at: almost 3 years ago - Stars: 406 - Forks: 198
WangXuan95/USTC-RVSoC
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
Language: SystemVerilog - Size: 62.2 MB - Last synced at: 7 months ago - Pushed at: about 2 years ago - Stars: 398 - Forks: 79
AngeloJacobo/UberDDR3
Opensource DDR3 Controller
Language: Verilog - Size: 64.6 MB - Last synced at: about 2 months ago - Pushed at: 5 months ago - Stars: 384 - Forks: 54
pavel-demin/red-pitaya-notes
Notes on the Red Pitaya Open Source Instrument
Language: Tcl - Size: 11 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 378 - Forks: 228
dalance/svlint
SystemVerilog linter
Language: Rust - Size: 4.35 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 365 - Forks: 43
dpretet/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Language: Verilog - Size: 1.01 MB - Last synced at: 6 months ago - Pushed at: over 1 year ago - Stars: 349 - Forks: 83
chipsalliance/sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
Language: SystemVerilog - Size: 13 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 347 - Forks: 84
mshr-h/vscode-verilog-hdl-support
HDL support for VS Code
Language: TypeScript - Size: 2.29 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 340 - Forks: 83
LeiWang1999/ZYNQ-NVDLA
NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
Language: Verilog - Size: 98 MB - Last synced at: 8 months ago - Pushed at: almost 2 years ago - Stars: 330 - Forks: 67
ZipCPU/sdspi
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
Language: Verilog - Size: 13.7 MB - Last synced at: 30 days ago - Pushed at: about 1 month ago - Stars: 324 - Forks: 50
nukeykt/Nuked-MD-FPGA
Mega Drive/Genesis core written in Verilog
Language: Verilog - Size: 4.71 MB - Last synced at: 4 months ago - Pushed at: about 1 year ago - Stars: 308 - Forks: 12
efabless/openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
Language: Python - Size: 31.4 MB - Last synced at: 4 months ago - Pushed at: 9 months ago - Stars: 305 - Forks: 65
Nic30/hdlConvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
Language: C++ - Size: 14.5 MB - Last synced at: about 2 months ago - Pushed at: 5 months ago - Stars: 304 - Forks: 77
f4pga/f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Language: Jupyter Notebook - Size: 9.52 MB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 295 - Forks: 115
WangXuan95/FPGA-SDcard-Reader
An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。
Language: Verilog - Size: 168 KB - Last synced at: 7 months ago - Pushed at: about 2 years ago - Stars: 290 - Forks: 66
jes/scamp-cpu
A homebrew 16-bit CPU with a homebrew Unix-like-ish operating system.
Language: Slash - Size: 41.9 MB - Last synced at: 21 days ago - Pushed at: almost 2 years ago - Stars: 289 - Forks: 7
JPShag/PCILeech-DMA-Firmware
The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com
Language: C - Size: 35.4 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 285 - Forks: 78
chipsalliance/f4pga-examples
Example designs showing different ways to use F4PGA toolchains.
Language: Verilog - Size: 113 MB - Last synced at: 7 months ago - Pushed at: over 1 year ago - Stars: 275 - Forks: 78
tymonx/logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Language: SystemVerilog - Size: 820 KB - Last synced at: 7 months ago - Pushed at: almost 6 years ago - Stars: 275 - Forks: 60
veripool/verilog-mode
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
Language: SystemVerilog - Size: 2.73 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 272 - Forks: 97
WangXuan95/FPGA-CAN
An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。
Language: Verilog - Size: 416 KB - Last synced at: 5 months ago - Pushed at: about 2 years ago - Stars: 272 - Forks: 82
ZipCPU/wbuart32
A simple, basic, formally verified UART controller
Language: Verilog - Size: 1.19 MB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 266 - Forks: 46
DegateCommunity/Degate
A modern and open-source cross-platform software for chips reverse engineering.
Language: C++ - Size: 658 MB - Last synced at: 4 months ago - Pushed at: 12 months ago - Stars: 264 - Forks: 33
viduraakalanka/HDL-Bits-Solutions
This is a repository containing solutions to the problem statements given in HDL Bits website.
Language: Verilog - Size: 47.9 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 262 - Forks: 79
WangXuan95/FPGA-UART
This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。
Language: Verilog - Size: 511 KB - Last synced at: about 1 month ago - Pushed at: about 2 years ago - Stars: 259 - Forks: 46
lastweek/fpga_readings
Recipe for FPGA cooking
Language: Verilog - Size: 51.8 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 258 - Forks: 56
0BAB1/HOLY_CORE_COURSE
Learn how to build our own RV32I core, verify it and actually use it. From scratch & with more than 200 pages of detailed tutorial with schemes & explanation.
Language: Python - Size: 23.1 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 251 - Forks: 30
zangman/de10-nano
Absolute beginner's guide to the de10-nano
Language: Shell - Size: 10.2 MB - Last synced at: 20 days ago - Pushed at: 9 months ago - Stars: 247 - Forks: 55
