systemverilog | Topic | Ecosyste.ms: Repos

Topic: "systemverilog"

chipsalliance/verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Language: C++ - Size: 12.8 MB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 1,617 - Forks: 250

clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

Language: Haskell - Size: 19.4 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1,535 - Forks: 163

pulp-platform/axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Language: SystemVerilog - Size: 9.86 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 1,366 - Forks: 310

hdl-util/hdmi

Send video/audio over HDMI on an FPGA

Language: SystemVerilog - Size: 4.13 MB - Last synced at: 11 days ago - Pushed at: over 1 year ago - Stars: 1,198 - Forks: 129

MikePopoloski/slang

SystemVerilog compiler and language services

Language: C++ - Size: 31.6 MB - Last synced at: about 5 hours ago - Pushed at: about 7 hours ago - Stars: 828 - Forks: 171

splinedrive/kianRiscV

RISC-V Linux SoC, marchID: 0x2b

Language: Assembly - Size: 198 MB - Last synced at: 5 months ago - Pushed at: 6 months ago - Stars: 816 - Forks: 58

veryl-lang/veryl

Veryl: A Modern Hardware Description Language

Language: Rust - Size: 80.3 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 783 - Forks: 44

olofk/edalize

An abstraction library for interfacing EDA tools

Language: Python - Size: 1.07 MB - Last synced at: 15 days ago - Pushed at: 16 days ago - Stars: 708 - Forks: 211

WangXuan95/FPGA-FOC

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

Language: Verilog - Size: 666 KB - Last synced at: 3 months ago - Pushed at: almost 2 years ago - Stars: 700 - Forks: 208

zachjs/sv2v

SystemVerilog to Verilog conversion

Language: Haskell - Size: 2.22 MB - Last synced at: 2 days ago - Pushed at: 3 months ago - Stars: 664 - Forks: 60

TerosTechnology/vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Language: VHDL - Size: 147 MB - Last synced at: 18 days ago - Pushed at: 19 days ago - Stars: 635 - Forks: 56

trivialmips/nontrivial-mips

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

Language: SystemVerilog - Size: 20.4 MB - Last synced at: 6 days ago - Pushed at: about 5 years ago - Stars: 603 - Forks: 102

openhwgroup/core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

Language: Assembly - Size: 112 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 575 - Forks: 251

dalance/svls

SystemVerilog language server

Language: Rust - Size: 918 KB - Last synced at: 3 days ago - Pushed at: 8 days ago - Stars: 528 - Forks: 31

dalance/sv-parser

SystemVerilog parser library fully compliant with IEEE 1800-2017

Language: Rust - Size: 48.2 MB - Last synced at: 20 days ago - Pushed at: 6 months ago - Stars: 449 - Forks: 61

pymtl/pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

Language: Python - Size: 5.39 MB - Last synced at: about 3 hours ago - Pushed at: 19 days ago - Stars: 427 - Forks: 56

rggen/rggen

Code generation tool for control and status registers

Language: Ruby - Size: 585 KB - Last synced at: 6 days ago - Pushed at: 27 days ago - Stars: 421 - Forks: 55

chipsalliance/Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Language: C++ - Size: 852 MB - Last synced at: 14 days ago - Pushed at: 15 days ago - Stars: 407 - Forks: 77

taichi-ishitani/tvip-axi

AMBA AXI VIP

Language: SystemVerilog - Size: 153 KB - Last synced at: 4 months ago - Pushed at: about 1 year ago - Stars: 401 - Forks: 112

WangXuan95/USTC-RVSoC

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

Language: SystemVerilog - Size: 62.2 MB - Last synced at: 5 months ago - Pushed at: almost 2 years ago - Stars: 398 - Forks: 79

dalance/svlint

SystemVerilog linter

Language: Rust - Size: 4.23 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 357 - Forks: 42

jamieiles/80x86

80186 compatible SystemVerilog CPU core and FPGA reference design

Language: C++ - Size: 1.39 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 357 - Forks: 51

chipsalliance/sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

Language: SystemVerilog - Size: 12.6 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 342 - Forks: 83

mshr-h/vscode-verilog-hdl-support

HDL support for VS Code

Language: TypeScript - Size: 2.28 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 335 - Forks: 82

Nic30/hdlConvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

Language: C++ - Size: 14.5 MB - Last synced at: 16 days ago - Pushed at: 2 months ago - Stars: 302 - Forks: 76

WangXuan95/FPGA-SDcard-Reader

An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

Language: Verilog - Size: 168 KB - Last synced at: 5 months ago - Pushed at: almost 2 years ago - Stars: 290 - Forks: 66

pulp-platform/cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Language: Verilog - Size: 42.6 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 279 - Forks: 75

tymonx/logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Language: SystemVerilog - Size: 820 KB - Last synced at: 5 months ago - Pushed at: almost 6 years ago - Stars: 275 - Forks: 60

veripool/verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

Language: SystemVerilog - Size: 2.73 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 272 - Forks: 97

WangXuan95/FPGA-CAN

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

Language: Verilog - Size: 416 KB - Last synced at: 3 months ago - Pushed at: almost 2 years ago - Stars: 272 - Forks: 82

MPSU/APS

Методические материалы по разработке процессора архитектуры RISC-V

Language: SystemVerilog - Size: 117 MB - Last synced at: 8 days ago - Pushed at: 19 days ago - Stars: 257 - Forks: 65

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Language: C++ - Size: 4.42 MB - Last synced at: 19 days ago - Pushed at: 19 days ago - Stars: 229 - Forks: 43

Nic30/hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Language: Python - Size: 19.4 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 214 - Forks: 29

WangXuan95/FPGA-FixedPoint

Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

Language: Verilog - Size: 75.2 KB - Last synced at: 5 days ago - Pushed at: almost 2 years ago - Stars: 204 - Forks: 35

mathis-s/SoomRV

A simple superscalar out-of-order RISC-V microprocessor

Language: SystemVerilog - Size: 11.7 MB - Last synced at: 5 months ago - Pushed at: 7 months ago - Stars: 202 - Forks: 16

Juniper/open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Language: Verilog - Size: 7.08 MB - Last synced at: 4 months ago - Pushed at: 11 months ago - Stars: 199 - Forks: 71

WangXuan95/FPGA-JPEG-LS-encoder

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

Language: Verilog - Size: 4.49 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 199 - Forks: 38

suoto/hdl_checker

Repurposing existing HDL tools to help writing better code

Language: Python - Size: 1.05 MB - Last synced at: 10 months ago - Pushed at: over 1 year ago - Stars: 192 - Forks: 22

WangXuan95/FPGA-ftdi245fifo

FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

Language: Verilog - Size: 250 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 189 - Forks: 59

openhwgroup/core-v-mcu

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

Language: SystemVerilog - Size: 35.9 MB - Last synced at: 8 days ago - Pushed at: about 2 months ago - Stars: 187 - Forks: 65

vproc/vicuna

RISC-V Zve32x Vector Coprocessor

Language: Assembly - Size: 765 KB - Last synced at: 8 days ago - Pushed at: almost 2 years ago - Stars: 187 - Forks: 56

taichi-ishitani/tnoc

Network on Chip Implementation written in SytemVerilog

Language: SystemVerilog - Size: 406 KB - Last synced at: 6 months ago - Pushed at: about 3 years ago - Stars: 171 - Forks: 46

vivekmalneedi/veridian

A SystemVerilog Language Server

Language: Rust - Size: 1010 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 164 - Forks: 18

SystemRDL/PeakRDL

Control and status register code generator toolchain

Language: Python - Size: 144 KB - Last synced at: about 7 hours ago - Pushed at: 16 days ago - Stars: 143 - Forks: 31

pulp-platform/croc

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

Language: SystemVerilog - Size: 106 MB - Last synced at: 12 days ago - Pushed at: 25 days ago - Stars: 135 - Forks: 68

loykylewong/FPGA-Application-Development-and-Simulation

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

Language: Scala - Size: 3.09 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 130 - Forks: 30

WangXuan95/FPGA-NFC

An FPGA-based NFC (RFID) reader with a simple circuit rather than RFID chips. 用FPGA+分立器件电路搭建一个NFC(RFID)读卡器，不需要专门的RFID芯片。

Language: Verilog - Size: 500 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 127 - Forks: 26

agalimberti/NoCRouter

RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni

Language: SystemVerilog - Size: 659 KB - Last synced at: 3 months ago - Pushed at: over 7 years ago - Stars: 126 - Forks: 41

WangXuan95/FPGA-SDfake

Imitate SDcard using FPGAs. 使用FPGA模拟伪装SD卡。

Language: Verilog - Size: 18.3 MB - Last synced at: 3 months ago - Pushed at: almost 2 years ago - Stars: 109 - Forks: 24

iammituraj/pequeno_riscv

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

Language: SystemVerilog - Size: 4.29 MB - Last synced at: 18 days ago - Pushed at: 19 days ago - Stars: 108 - Forks: 9

pulp-platform/carfield

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

Language: Tcl - Size: 6.32 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 108 - Forks: 22

trivialmips/TrivialMIPS

MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support

Language: SystemVerilog - Size: 84.3 MB - Last synced at: 6 days ago - Pushed at: over 6 years ago - Stars: 107 - Forks: 35

WangXuan95/FPGA-SATA-HBA

A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。

Language: SystemVerilog - Size: 5.06 MB - Last synced at: 3 months ago - Pushed at: almost 2 years ago - Stars: 105 - Forks: 35

intel/rohd-hcl

A hardware component library developed with ROHD.

Language: Dart - Size: 40.8 MB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 102 - Forks: 33

WangXuan95/FPGA-MPEG2-encoder

FPGA-based high performance MPEG2 encoder for video compression. 基于FPGA的高性能MPEG2视频编码器，可实现视频压缩。

Language: Verilog - Size: 22.2 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 97 - Forks: 17

gupta409/Processor-UVM-Verification

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

Language: Verilog - Size: 355 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 95 - Forks: 33

clin99/awesome-eda

Size: 51.8 KB - Last synced at: 5 days ago - Pushed at: about 6 years ago - Stars: 93 - Forks: 17

ben-marshall/verilog-vcd-parser

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

Language: C++ - Size: 76.2 KB - Last synced at: 5 months ago - Pushed at: over 3 years ago - Stars: 92 - Forks: 36

PrincetonUniversity/AutoSVA

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

Language: Python - Size: 57 MB - Last synced at: 2 months ago - Pushed at: over 1 year ago - Stars: 84 - Forks: 26

WangXuan95/FPGA-SDcard-Reader-SPI

An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线)，可以从FAT16或FAT32格式的SD卡中读取文件。

Language: Verilog - Size: 3.09 MB - Last synced at: 3 months ago - Pushed at: almost 2 years ago - Stars: 83 - Forks: 20

mmxsrup/axi4-interface

AXI4 and AXI4-Lite interface definitions

Language: SystemVerilog - Size: 31.3 KB - Last synced at: 11 months ago - Pushed at: almost 5 years ago - Stars: 82 - Forks: 27

dpretet/svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Language: Python - Size: 755 KB - Last synced at: 5 days ago - Pushed at: 11 months ago - Stars: 80 - Forks: 17

KastnerRG/cgra4ml

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

Language: SystemVerilog - Size: 12.5 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 79 - Forks: 11

pulp-platform/pulp_soc

pulp_soc is the core building component of PULP based SoCs

Language: Python - Size: 1.13 MB - Last synced at: 5 months ago - Pushed at: 6 months ago - Stars: 79 - Forks: 82

BrianHGinc/BrianHG-DDR3-Controller

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

Language: SystemVerilog - Size: 9.94 MB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 79 - Forks: 34

hdl-util/sdram-controller

Generic FPGA SDRAM controller, originally made for AS4C4M16SA

Language: Verilog - Size: 1.54 MB - Last synced at: 6 months ago - Pushed at: about 5 years ago - Stars: 79 - Forks: 11

dshekhalev/FEC

FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)

Language: SystemVerilog - Size: 1.36 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 78 - Forks: 25

unixb0y/SystemVerilogSHA256

SHA256 in (System-) Verilog / Open Source FPGA Miner

Language: SystemVerilog - Size: 148 KB - Last synced at: 5 months ago - Pushed at: over 7 years ago - Stars: 78 - Forks: 26

cristian-mattarei/CoSA

CoreIR Symbolic Analyzer

Language: Python - Size: 7.98 MB - Last synced at: 5 days ago - Pushed at: almost 5 years ago - Stars: 74 - Forks: 18

mikeroyal/Verilog-SystemVerilog-Guide

Verilog/SystemVerilog Guide

Language: SystemVerilog - Size: 19.5 KB - Last synced at: 14 days ago - Pushed at: over 1 year ago - Stars: 72 - Forks: 10

SystemRDL/PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Language: Python - Size: 935 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 71 - Forks: 48

chili-chips-ba/openCologne

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://nanoxplore.com

Language: Verilog - Size: 296 MB - Last synced at: 6 days ago - Pushed at: 15 days ago - Stars: 68 - Forks: 7

sifferman/labs-with-cva6

Advanced Architecture Labs with CVA6

Language: SystemVerilog - Size: 311 KB - Last synced at: 11 days ago - Pushed at: over 1 year ago - Stars: 67 - Forks: 27

oddball/ipxact2systemverilog

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

Language: Python - Size: 4.78 MB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 63 - Forks: 21

wyvernSemi/vproc

Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments

Language: VHDL - Size: 13.9 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 62 - Forks: 11

varunnagpaal/Digital-Hardware-Modelling

Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)

Language: VHDL - Size: 45.6 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 62 - Forks: 13

taneroksuz/fpu

IEEE 754 single and double precision floating point library in systemverilog and vhdl

Language: VHDL - Size: 292 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 61 - Forks: 10

suoto/vim-hdl 📦

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

Language: Python - Size: 460 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 61 - Forks: 6

chili-chips-ba/openeye-CamSI

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.

Language: SystemVerilog - Size: 276 MB - Last synced at: 6 days ago - Pushed at: 2 months ago - Stars: 60 - Forks: 15