hardware-description-language | Topic

Topic: "hardware-description-language"

clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

Language: Haskell - Size: 19.6 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1,485 - Forks: 158

drom/awesome-hdl

Hardware Description Languages

Size: 135 KB - Last synced at: 10 days ago - Pushed at: 2 months ago - Stars: 1,011 - Forks: 97

JulianKemmerer/PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

Language: VHDL - Size: 76.1 MB - Last synced at: 7 days ago - Pushed at: 23 days ago - Stars: 644 - Forks: 50

WangXuan95/BSV_Tutorial_cn

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

Language: Bluespec - Size: 31.1 MB - Last synced at: 1 day ago - Pushed at: over 1 year ago - Stars: 566 - Forks: 44

jofrfu/tinyTPU

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Language: VHDL - Size: 1.42 MB - Last synced at: 15 days ago - Pushed at: over 6 years ago - Stars: 452 - Forks: 64

SystemRDL/systemrdl-compiler

SystemRDL 2.0 language compiler front-end

Language: C++ - Size: 2.53 MB - Last synced at: 4 days ago - Pushed at: about 1 month ago - Stars: 250 - Forks: 70

cucapra/filament

Fearless hardware design

Language: Verilog - Size: 4.85 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 175 - Forks: 9

mit-plv/kami

A Platform for High-Level Parametric Hardware Specification and its Modular Verification

Language: Coq - Size: 4.67 MB - Last synced at: 17 days ago - Pushed at: 7 months ago - Stars: 151 - Forks: 26

mit-plv/koika

A core language for rule-based hardware design 🦑

Language: Coq - Size: 4.81 MB - Last synced at: 17 days ago - Pushed at: 6 months ago - Stars: 148 - Forks: 12

SystemRDL/PeakRDL

Control and status register code generator toolchain

Language: Python - Size: 159 KB - Last synced at: 4 days ago - Pushed at: about 1 month ago - Stars: 123 - Forks: 27

asyncvlsi/act

ACT hardware description language and core tools.

Language: C++ - Size: 4.89 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 108 - Forks: 27

cyber-anubis/The-HACK-General-Purpose-Computer

Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone computer hardware platform; Including Virtual machine,Compiler and Operating system.

Language: Python - Size: 151 KB - Last synced at: 2 months ago - Pushed at: over 4 years ago - Stars: 99 - Forks: 5

pc2/sus-compiler

A new Hardware Design Language that keeps you in the driver's seat

Language: Rust - Size: 17.1 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 78 - Forks: 5

mikeroyal/VHDL-Guide

VHDL Guide

Language: VHDL - Size: 135 KB - Last synced at: 10 days ago - Pushed at: over 3 years ago - Stars: 60 - Forks: 8

JeffDeCola/my-verilog-examples

A place to keep my synthesizable verilog examples.

Language: Verilog - Size: 13.7 MB - Last synced at: about 22 hours ago - Pushed at: about 23 hours ago - Stars: 36 - Forks: 11

aofarmakis/Nibbling-bits

Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.

Language: Verilog - Size: 4.01 MB - Last synced at: 12 days ago - Pushed at: 5 months ago - Stars: 32 - Forks: 0

tharunchitipolu/Dadda-Multiplier-using-CSA

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

Language: Verilog - Size: 19.5 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 32 - Forks: 6

drom/reqack

🔁 elastic circuit toolchain

Language: JavaScript - Size: 275 KB - Last synced at: 4 days ago - Pushed at: 5 months ago - Stars: 30 - Forks: 5

broccolimicro/loom

design and verification of asynchronous circuits

Language: Python - Size: 9.93 MB - Last synced at: 10 days ago - Pushed at: 25 days ago - Stars: 19 - Forks: 0

GSimas/INE5406

📚Repositório da Disciplina INE5406 - Sistemas Digitais

Language: HTML - Size: 341 MB - Last synced at: about 1 year ago - Pushed at: almost 7 years ago - Stars: 15 - Forks: 1

chaseruskin/legoHDL

An experimental package manager and development tool for Hardware Description Languages (HDL).

Language: Python - Size: 3.9 MB - Last synced at: 2 days ago - Pushed at: about 3 years ago - Stars: 14 - Forks: 2

spacetimeengineer/mupy

Python Manufacturing Utility or "mupy" is a powerful new digital-twin technology. In it's essence, a new way to think about design, physical hardware, advanced assemblies, innovative technologies, or most generally, system design.

Language: Python - Size: 65 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 12 - Forks: 2

fayizferosh/yosys-tcl-ui-report

5 Day TCL begginer to advanced training workshop by VSD

Language: Verilog - Size: 1.17 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 12 - Forks: 0

povik/fold

high abstraction synthesis

Language: Python - Size: 765 KB - Last synced at: 7 days ago - Pushed at: about 1 year ago - Stars: 10 - Forks: 0

VitorgsRuffo/Building-The-Hack-Computer

This is a personal project which purpose is to learn computer architecture by implementing the Hack Computer.

Language: Scilab - Size: 281 KB - Last synced at: 11 months ago - Pushed at: over 3 years ago - Stars: 10 - Forks: 2

gergoerdi/retroclash-lib

Library code for upcoming RetroClash book

Language: Haskell - Size: 248 KB - Last synced at: 2 days ago - Pushed at: about 2 months ago - Stars: 9 - Forks: 7

tilk/yieldfsm

YieldFSM, a DSL for describing finite state machines in Clash

Language: Haskell - Size: 274 KB - Last synced at: 12 months ago - Pushed at: over 2 years ago - Stars: 8 - Forks: 0

tharunchitipolu/Multi-operations-toolbox-with-baugh-wooley-multiplier

Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier

Language: Verilog - Size: 52.7 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 7 - Forks: 1

estradjm/Code-Portfolio

Code Portfolio -- Collection of Interesting CS and ECE Projects in different languages (C, C++, Python, CPU & GPU Parallel Paradigms, MATLAB, and VHDL) and target hardware with technical reports, and my Vim Config

Language: C - Size: 146 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 7 - Forks: 1

jpt13653903/ALCHA

A New Programming Language for FPGA Projects

Language: C++ - Size: 3.99 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 6 - Forks: 0

m47812/HDL_Converter

A simple tool that can be used to convert the header syntax of a verilog module or VHDL entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches.

Language: C# - Size: 366 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 6 - Forks: 2

david-palma/mips-32bit

Microprocessor without Interlocked Pipelined Stages (MIPS) architectures implemented in single-cycle and multi-cycle formats.

Language: VHDL - Size: 366 KB - Last synced at: 9 days ago - Pushed at: almost 6 years ago - Stars: 6 - Forks: 1

Choaib-ELMADI/getting-started-with-verilog

Getting started with Verilog: Hardware Description Language for digital design.

Language: Verilog - Size: 9.87 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 5 - Forks: 0

meiniKi/logIP

Logic Analyzer IP Core

Language: SystemVerilog - Size: 306 KB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 5 - Forks: 1

lazyoracle/vhdl-processor

An 8-bit processor in VHDL based on a simple instruction set

Language: VHDL - Size: 209 KB - Last synced at: 10 months ago - Pushed at: about 6 years ago - Stars: 5 - Forks: 0

vikrrrr/croc

ChaCha stream cipher modules written in Python, described using Amaranth.

Language: Python - Size: 19.5 KB - Last synced at: about 1 year ago - Pushed at: about 3 years ago - Stars: 4 - Forks: 0

Eforen/FlowHS

Flow Based Hardware Simulator

Language: JavaScript - Size: 8.07 MB - Last synced at: 28 days ago - Pushed at: about 4 years ago - Stars: 4 - Forks: 0

AkhilRai28/Single-Port-RAM

This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.

Language: Verilog - Size: 68.4 KB - Last synced at: 19 days ago - Pushed at: 8 months ago - Stars: 3 - Forks: 0

axvr/gait

An experimental, interactive, object-oriented, hardware description language (HDL).

Language: Clojure - Size: 33.2 KB - Last synced at: 2 days ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 0

ArvinDelavari/Digital-Circuits-Verilog

Sample Verilog codes for digital circuits

Language: HTML - Size: 9.31 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 0

ADolbyB/vhdl-fpga-nexys-a7

A collection of code from CDA 4240C: Design of Digital System and Lab

Language: VHDL - Size: 5.58 MB - Last synced at: about 1 month ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 0

aesthet1c0der/Verilog-projects

ALU (Arithmetic and Logic Unit), Ripple carry adder, Half adder and full adder are designed using all 3 styles (structural, behavioral, dataflow) and tested by generating stimulus using testbench

Language: Verilog - Size: 21.5 KB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 0

gholomia/Freeman

The digital design of computer systems course project, named freeman with respect to the Ross Freeman, the inventor of FPGA, under supervision of Dr. M. Saheb Zamani.

Language: VHDL - Size: 21.2 MB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 3 - Forks: 1

jamestiotio/compstruct

SUTD 2020 50.002 Computation Structures Code Dump

Language: C - Size: 89.7 MB - Last synced at: 12 months ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 0

Daymorelah/vendingMachine

A simple VHDL code that describes the hardware needed to implement a vending machine

Language: VHDL - Size: 485 KB - Last synced at: 5 months ago - Pushed at: over 7 years ago - Stars: 3 - Forks: 1

helcsnewsxd/famaf-computer_science-computer_architecture 📦

Laboratorios, prácticos y teóricos de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)

Language: SystemVerilog - Size: 6.83 MB - Last synced at: about 2 months ago - Pushed at: 9 months ago - Stars: 2 - Forks: 0

helcsnewsxd/famaf-computer_science-computer_architecture-lab2 📦

Laboratorio 2 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)

Language: Assembly - Size: 1.85 MB - Last synced at: about 2 months ago - Pushed at: 9 months ago - Stars: 2 - Forks: 0

chykon/svart

Svart is an embedded (in Dart) domain-specific language for describing binary circuits, generating a strict subset of SystemVerilog and easily interacting with external tools.

Language: Dart - Size: 81.1 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

FaresAtef1/AES-Advanced-Encryption-Standard

256-bit Advanced Encryption Standard Implemented with Verilog HDL.

Language: Verilog - Size: 26.4 KB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 2

lironmiz/nand2tetrisCourse

acadamic course in campus il about building a modern computer from basic logic gates such as "nand" to a general computer architecture that is designed execute any program such as "Tetris". and also building assambler

Language: Scilab - Size: 101 KB - Last synced at: 2 days ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 0

maehw/wokwi-lookup-table-generator

Generator for wokwi schematics that implement lookup tables in conjunctive normal form (CNF), i.e. with AND and OR gates

Language: Python - Size: 61.5 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 1

harshbhosale01/HDLBits

In this repository, I will be adding my solutions to HDLBits practice problems

Language: Verilog - Size: 4.88 KB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 0

sohelrana-aiub/Field-Programmable-Gate-Array-FPGAs

Digital Design with System(Verilog HDL,VHDL , System Verilog & FPGAs)

Size: 112 KB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 0

AhmadrezaHadi/MIPS-Architecture-Using-Verilog

FPGA Final Project

Language: C - Size: 1020 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

EngineeringSoftware/hdlp 📦

Code and data for "On the Naturalness of Hardware Descriptions" in ESEC/FSE'20

Language: Java - Size: 40.4 MB - Last synced at: 29 days ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 2

Mehrdadghassabi/Dosage_cpu Fork of ZahraAbtahi/Dosage-Cpu

dosage is a 20bit single cycle RISC cpu based on harvard architecture

Language: Python - Size: 1.2 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 0

feliposz/nand2tetris

Exercises and notes on the course Build a Modern Computer from First Principles

Language: Hack - Size: 767 KB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 1

gvilardefarias/Hardware-Data-Structures

A systemverilog implementation of the data structures: priority queue, queue and stack

Language: SystemVerilog - Size: 9.77 KB - Last synced at: over 1 year ago - Pushed at: about 5 years ago - Stars: 2 - Forks: 1

yh08037/Verilog-HDL

[2019.1] 논리회로 이론 및 설계 Verilog 문법 정리

Language: Verilog - Size: 3.91 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 0

abiduzz420/nand2tetris

building a computer

Language: Assembly - Size: 51 MB - Last synced at: 10 months ago - Pushed at: almost 6 years ago - Stars: 2 - Forks: 0

Joanna20Carrion/Joanna20Carrion

Size: 2.44 MB - Last synced at: 2 days ago - Pushed at: 3 days ago - Stars: 1 - Forks: 0

icarogabryel/flote

Flote is a HDL and Python framework for simulation. Designed to be friendly, simple, and productive. Easy to use and learn.

Language: Python - Size: 254 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1 - Forks: 0

nathsou/yodl

Yet anOther hardware Description Language

Language: MoonBit - Size: 2.79 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 1 - Forks: 0

Quanoom/FrequencyDivider

verilog code for frequency divider circuit implemented with verilog hdl

Language: Verilog - Size: 8.79 KB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 1 - Forks: 0

VicoHBB/Verilator-SV-Template

This project template is designed to streamline the development of SystemVerilog projects using Verilator, GTKWave, and Make. The template includes a Makefile with various recipes for compiling, simulating, and visualizing the design. It also includes a directory structure for organizing the HDL files, test benches, and simulation waveforms.

Language: SystemVerilog - Size: 62.5 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0

Quanoom/SequenceDetector

11001 sequence detector

Language: Verilog - Size: 10.7 KB - Last synced at: 7 days ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

MohammedS2lah/HDLBits_Verilog_Tutorials

Welcome to my repository, where I provide solutions to Verilog challenges from the HDLBits website

Language: Verilog - Size: 378 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

wojciechmarek/my-fpga-journey

A set of code examples for Tang Nano 1K FPGA board.

Language: VHDL - Size: 417 KB - Last synced at: 29 days ago - Pushed at: 7 months ago - Stars: 1 - Forks: 0

helcsnewsxd/famaf-computer_science-computer_architecture-lab1 📦

Laboratorio 1 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)

Language: SystemVerilog - Size: 2.55 MB - Last synced at: about 2 months ago - Pushed at: 9 months ago - Stars: 1 - Forks: 0

SauravMaheshkar/verilog-template

❄️ Template for Verilog Projects using iverilog and gtkwave (nix devShell supported)

Language: Makefile - Size: 15.6 KB - Last synced at: about 9 hours ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0

Qyt0109/My-own-RISC-V-ISA-based-CPU-on-FPGAs

RISC-V is an open-source instruction set architecture (ISA), enabling the implementation of central processing units (CPUs) or system-on-a-chip (SoC) designs without licensing fees. This makes it highly favored among FPGA enthusiasts for softcore processor implementations.

Language: Verilog - Size: 7.18 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

Raveem13/HDLbits-practice-solution

This is a repository containing my solutions to the problem statements given on HDLBits website.

Language: Verilog - Size: 150 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

AzazHassankhan/VHDLCodeCraft

Welcome to the "VHDL_Coding_Designs" repository, your gateway to the world of VHDL (VHSIC Hardware Description Language) and digital design. This is the space where hardware meets innovation, and digital concepts come to life. 🌐

Size: 182 KB - Last synced at: about 1 month ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

jamestiotio/ehp

SUTD ISTD 2020 Computation Structures Electronic Hardware 1D Project

Language: Python - Size: 31.5 MB - Last synced at: 12 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

UFESL/.github

Introduction about Embedded systems lab, University of Florida

Size: 6.84 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 1

miltosmac/TCAD

An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers on FPGAs

Language: C++ - Size: 246 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

FaithGriffin/CSARCH1_HDLProject2

Verilog structural model HDL program

Language: Verilog - Size: 119 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

FaithGriffin/CSARCH1_HDLProject3

Verilog structural model HDL program

Language: Verilog - Size: 109 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

FaithGriffin/CSARCH1_HDLProject1

Verilog behavioral model HDL program

Language: Verilog - Size: 59.6 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

LorenzoServolini/Minimum-voltage

Description and synthesis (Register-transfer level) of hardware that takes three voltages as input via A/D converters (using the soc/eoc handshake) and returns the minimum value to the consumer using dav/rfd handshake.

Language: Verilog - Size: 21.5 KB - Last synced at: 5 months ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

maxkl/hdl-compiler

Compiler for a self-invented hardware description language (mirrors https://gitlab.com/maxkl2/hdl-compiler)

Language: Rust - Size: 201 KB - Last synced at: about 1 year ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

pawan-nirpal-031/ComputerArchitecture-MicroprocessorDesign

Basic Microprocessor Design in HDLs like Verilog.

Language: C++ - Size: 5.66 MB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

rishabh-panda/VLSI-Laboratory

Design and Testbench codes.

Language: Verilog - Size: 396 KB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

dlesbre/cephalopode

The cephalopod IoT processor and the bifrost compiler

Language: Haskell - Size: 315 KB - Last synced at: 15 days ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 1

shivamsingha/hardware-lab-verilog

Verilog sources for Hardware Lab Assignments

Language: Verilog - Size: 294 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

mateusxxlima/hardware-description

Hardware description project in verilog language implemented in the area of Digital Systems in the third semester of the Computer Science course at UFFS

Language: Verilog - Size: 1.95 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

jricaldi95/DAS

VHDL video game and examples of drivers dumped on Spartan3 FPGA

Language: C - Size: 4.39 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 1 - Forks: 0

Sh3b0/FPGA-Snake

7-segment snake using a microcontroller

Language: SystemVerilog - Size: 6.86 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

joe-legg/miniHDL

A small toy hardware description language.

Language: C++ - Size: 126 KB - Last synced at: about 1 year ago - Pushed at: almost 6 years ago - Stars: 1 - Forks: 1

EnricoRuggiano/stm32-watchdogs

Language: SystemVerilog - Size: 31.3 KB - Last synced at: almost 2 years ago - Pushed at: about 6 years ago - Stars: 1 - Forks: 0

Razer6/iverilog Fork of steveicarus/iverilog

Icarus Verilog

Language: C++ - Size: 21.3 MB - Last synced at: 9 months ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

vaddya/hdl 📦

Hardware Description Languages

Language: C - Size: 7.61 MB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0