digital-logic-design | Topic | Ecosyste.ms: Repos

Topic: "digital-logic-design"

logisim-evolution/logisim-evolution

Digital logic design tool and simulator

Language: Java - Size: 108 MB - Last synced at: 4 days ago - Pushed at: 9 days ago - Stars: 5,739 - Forks: 726

yupferris/kaze 📦

An HDL embedded in Rust.

Language: Rust - Size: 319 KB - Last synced at: 19 days ago - Pushed at: over 1 year ago - Stars: 198 - Forks: 9

raycar5/logicsim

Composable digital logic simulation in Rust!

Language: Rust - Size: 539 KB - Last synced at: about 1 month ago - Pushed at: over 4 years ago - Stars: 32 - Forks: 1

MuxammilSidd/FAST-KHI-Semester-2

FAST NUCES Karachi - BSCS Second Semester Repository | Access notes, assignments, past papers, & more. For queries or suggestions, contact [email protected].

Language: C++ - Size: 1.1 GB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 26 - Forks: 6

This repository includes academic notes, study materials, and resources from B.Tech (Hons) in CSE, specializing in Artificial Intelligence and Data Science. It features question papers, proprietary study guides, and resources to support learning in these fields.

Language: HTML - Size: 2.41 GB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 22 - Forks: 2

shrine-maiden-heavy-industries/torii-hdl

A modern hardware definition language and toolchain based on Python

Language: Python - Size: 1.16 GB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 16 - Forks: 1

Amey-Thakur/DIGITAL-LOGIC-DESIGN-AND-ANALYSIS-AND-DIGITAL-SYSTEM-LAB

CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] <Semester III>

Size: 185 MB - Last synced at: 3 months ago - Pushed at: about 1 year ago - Stars: 10 - Forks: 1

SM2A/University_Projects

🎓💻All of my projects at University of Tehran

Size: 38.1 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 8 - Forks: 0

harismuneer/Car-Parking-Controller

🚗 A Car Parking Simulator made in LogicWorks 5 as a final project for the course "Digital Logic Design (EE227)"

Size: 1.08 MB - Last synced at: 3 months ago - Pushed at: 4 months ago - Stars: 7 - Forks: 5

rohankalbag/vlsi-design

VLSI Design - Autumn Semester 2022 - Indian Institute of Technology Bombay

Language: VHDL - Size: 5.68 MB - Last synced at: 3 months ago - Pushed at: about 2 years ago - Stars: 7 - Forks: 0

hasnainroopawalla/circuit-sim

Digital logic gate simulator using React, TypeScript and p5.js

Language: TypeScript - Size: 2.11 MB - Last synced at: about 1 month ago - Pushed at: 4 months ago - Stars: 6 - Forks: 1

Multimedia-Processing/Digital-Logic-Design

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

Language: Verilog - Size: 181 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 6 - Forks: 2

skamal16/Mobile-Trainer-Board

My second semester project for my object-oriented programming course. A simulation game for the lab work done in my second semester Digital Logic Design course.

Language: Java - Size: 5.14 MB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 6 - Forks: 0

azizi-zahra/simple-vending-machine

DLD Project - A simple vending machine simulation with Verilog (Spring 2024)

Language: Verilog - Size: 1.87 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 4 - Forks: 0

umarwaseeem/BS-CS-Semester-2

Semester 2 course material for BS Computer Science at Fast National University Of Computer And Emerging Sciences

Size: 35.8 MB - Last synced at: 10 months ago - Pushed at: over 2 years ago - Stars: 4 - Forks: 2

Harsh-Avinash/DLD-Lab-Simulations

CSE 1003 Digital Logic And Design's Lab Components all packed up in one neat and arranged repository

Language: AGS Script - Size: 5 MB - Last synced at: about 1 year ago - Pushed at: almost 4 years ago - Stars: 4 - Forks: 0

bryan-hoang/elec-271-digital-systems-labs 📦

VHDL Code for Labs done in a 2nd year engineering Digital Systems course (ELEC 271) at Queen's University.

Language: VHDL - Size: 10.7 KB - Last synced at: 4 days ago - Pushed at: 6 months ago - Stars: 3 - Forks: 1

stineje/dldfall2023

This repository contains information about Digital Logic Design (ecen 3233) laboratory elements for Fall 2023.

Language: TeX - Size: 62.1 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 3 - Forks: 3

ShashankVM/generic_systemverilog_designs_library

A library of useful, fully parameterized RTL designs implemented in SystemVerilog.

Language: SystemVerilog - Size: 39.1 KB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 1

ChaminduS/Building-a-RISC-V-CPU-Core

This repository contains my work in completing the course titled "Building a RISC-V CPU Core" offered by the Linux Foundation through edX.

Size: 175 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 3 - Forks: 0

Bh4r4t/32-bit-Divider

32-bit Divider circuit implemented using Verilog

Language: Verilog - Size: 8.79 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 0

BunyaminYavuz/university_lectures_source

Sources of some of the courses I took during my undergraduate education in Computer Engineering.

Size: 102 MB - Last synced at: 3 months ago - Pushed at: almost 2 years ago - Stars: 2 - Forks: 0

PashaBarahimi/Digital-Logic-Design-Lab-Experiments

Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.

Language: Verilog - Size: 9.9 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 2

pjbk/Logic-Circuit-Design-Lab-Work-

Digital Logic Design (DLD) is a fundamental subject for the engineering students worldwide. Well, many students find it difficult to design the digital circuits properly while pursuing the DLD course in colleges or universities. Therefore, I will try to assist those students by sharing my lab works with them.

Size: 1.77 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 1

Greathoney/Verilog_TermProject

베릴로그 텀 프로젝트: 추상전략게임인 tic tac toe를 구현합니다.

Language: Verilog - Size: 3.72 MB - Last synced at: about 1 year ago - Pushed at: almost 6 years ago - Stars: 2 - Forks: 2

danielkim802/PyLogic

Python digital logic library

Language: Python - Size: 63.5 KB - Last synced at: over 1 year ago - Pushed at: almost 7 years ago - Stars: 2 - Forks: 1

SiluPanda/8-bit-wallace-tree-multipier

This is a 8 bit binary number multiplier using wallace tree.

Language: VHDL - Size: 7.81 KB - Last synced at: over 1 year ago - Pushed at: about 7 years ago - Stars: 2 - Forks: 1

atrejojr/Projects

Projects made while at BU

Size: 6.35 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 0

ihdavjar/EEL2020_Project_EVM

This repo contains the EEL2020 course project, which was instructed to be made in hindi.

Language: HTML - Size: 2.15 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 1 - Forks: 0

SarwanShah/HU_2017_8-bit-ALU-Using-Logic-Gates

This project presents the hardware design for an 8-bit arithmetic logic unit

Size: 377 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

SarwanShah/HU_2019_8-Bit-Arithmetic-Operations-on-Atmega328

Programming an 8-bit binary calculator using AVR Assembly

Language: Assembly - Size: 154 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

PATEL96/CollegeWork

All codes Done during my Practical Session with Some Amazing Concepts

Language: Java - Size: 10.7 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 1 - Forks: 0

burhanahmed1/BitCalculator

BitCalculator is used for bitwise arithematic operations like addition, subtraction, multiplication etc.

Size: 6.77 MB - Last synced at: 3 months ago - Pushed at: 11 months ago - Stars: 1 - Forks: 0

PeiqiLi-Github/CSE-2301-Principles-and-Practice-of-Digital-Logic-Design-UConn

CSE2301 Principles and Practice of Digital Logic Design UConn

Language: Python - Size: 49 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

SharadaShehan/Nanoprocessor_Design

Xilinx Vivado project for nanoprocessor designing with VHDL

Language: VHDL - Size: 14.7 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

Dare-marvel/Digital-System-and-Microprocessors

Contains Notes and Experiments of DSM

Size: 107 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

Ammar-Bin-Amir/Traffic_Control_System

One Way Traffic Flow System

Size: 16.7 MB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 2

MisaghM/Digital-Logic-Design-Lab-Experiments Fork of PashaBarahimi/Digital-Logic-Design-Lab-Experiments

Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.

Size: 9.89 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

pawan-nirpal-031/ComputerArchitecture-MicroprocessorDesign

Basic Microprocessor Design in HDLs like Verilog.

Language: C++ - Size: 5.66 MB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

djzenma/A-Star-Integrated-Circuit-Routing

A Star Algorithm used to route pins using Metal 1, Metal 2 and Metal 3 wires.

Language: Java - Size: 2.27 MB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

SM2A/Digital_Logic_Design_Lab_Course_Projects

🎓💻University of Tehran Digital Logic Design Lab Course Projects - Spring 2021

Language: Verilog - Size: 31.4 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

axelitama/Progetto-Reti-Logiche-2020-2021

Final project of the course Reti Logiche (Digital Logic Design) at Politecnico di Milano

Language: VHDL - Size: 777 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

ahmedishraq/CSE260-LAB-Circuit

CSE260: Digital Logic Design Lab

Size: 117 KB - Last synced at: about 2 months ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

hardik01shah/digital-design-project-2020

This was my semester project for the Digital Design course 2020 (Fall). Simulated a door counter in logisim.

Size: 3.33 MB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

LandryNorris/Digital-Circuit-Simulator

Simulates digital circuitry.

Language: Java - Size: 132 KB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

Boyzmsc/digital-logic-design

Learning Digital-logic-design

Language: C++ - Size: 1.59 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

hansinahuja/Digital-Logic-Design

Codes written by me in my Digital Logic Design course.

Language: HTML - Size: 1 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

Ajarlin/CS211-Computer-Architecture

Computer Architecture: 01:198:211 This course covers the fundamental issues in the design of modern computer systems, including the design and implementation of key hardware components such as the processor, memory, and I/O devices, and the software/hardware interface.

Language: C - Size: 1.87 MB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

SConsul/EE214

Code Archive for Digital Lab (EE 214 @ IITB, Spring 2017)

Language: VHDL - Size: 369 KB - Last synced at: about 2 years ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0

davismariotti/HelicopterGame

A helicopter game written for the Nexys 4 DDR Board in VHDL

Language: VHDL - Size: 12 MB - Last synced at: over 1 year ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 3

yashkathe/4-bit-CPU-from-scratch

A step-by-step journey into building a 4 bit CPU from scratch

Language: JavaScript - Size: 766 KB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0

Gowtham011224/hardware-projects

Language: C++ - Size: 9.34 MB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 0 - Forks: 0

aadium/tic-tac-toe

A hardware-based Tic-Tac-Toe game built from the ground up using electronics and logical design principles.

Language: C++ - Size: 223 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

abdullahdarofficial/DIGITAL-LOGIC-DESIGN

🔢 **Digital Logic Design** – A comprehensive repository featuring lecture notes, textbook references, and study materials for Digital Logic Design. Includes chapters from *Logic & Computer Design Fundamentals* by Morris Mano, covering essential concepts like Boolean algebra, combinational circuits, sequential logic, and more. Perfect for students

Size: 12.8 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

ewdlop/Hardware-Notes

Electrical Enignnering

Language: VHDL - Size: 69.8 MB - Last synced at: about 15 hours ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

VarshithGovi/Half-Subtractor-Design-Verilog

Gate-level implementation of a half-subtractor using Verilog, featuring a comprehensive testbench, truth table validation, and waveform analysis for beginners in digital design.

Language: Verilog - Size: 20.5 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

5y3b/Tabular-Method

Quine-McCluskey Minimization Technique (Tabular-Method) Digital Logic Design

Language: Python - Size: 5.86 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

VarshithGovi/Full-Adder-Design-Verilog

Gate-level implementation of a full-adder using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.

Language: Verilog - Size: 11.7 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

VarshithGovi/2-to-1-Multiplexer-Design-Verilog

Gate-level implementation of a 2-to-1 multiplexer using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.

Language: Verilog - Size: 17.6 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

npwitk/EES270-Digital-Circuits-Laboratory-VHDL

A repository of VHDL code from the EES270 Digital Circuits Laboratory course at SIIT, including implementations and simulations for various digital circuits designed during lab sessions.

Language: VHDL - Size: 14.6 KB - Last synced at: 2 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

h0nt3d/modulo2345UpDownCounter

A counter written in VHDL that has been designed to count in radix 8 up and down from 0 to 2344 in radix 14 while displaying the counting on 4 Seven Segment Displays

Language: VHDL - Size: 8.79 MB - Last synced at: 3 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

TeslaNeuro/Artifical-Neuron-Design-Using-Digital-Electronics

Development of an Artifical Neuron purely using only Digital Electronics for a simple traffic light controller application.

Size: 322 KB - Last synced at: about 2 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

gcardi/HDL

Informational materials for a course on logic networks, HDLs and programmable logic arrays (FPGAs).

Size: 34.4 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

Ashritv/Building-a-RISC-V-CPU-Core Fork of stevehoover/LF-Building-a-RISC-V-CPU-Core

This Repository Contains my TL-Verilog code Developed During Completion of Course Titled "Building a RISC-V CPU Core" offered by the Linux Foundation through edX

Language: TL-Verilog - Size: 318 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

shahriar-raj/CSE_206-Digital-Logic-Design-Sessional

This repository contains all home and lab assignments for the CSE 206: Digital Logic Design Sessional course, part of our Term-1, Level-2 curriculum. It applies theories from CSE 205 to implement digital logics and practically experience them.

Size: 10.2 MB - Last synced at: 3 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

brucesdad13/3-Input_Odd_Parity

This repository contains the Arduino code and schematic for a three-bit binary odd parity generator. The project uses 7400 series TTL to construct the parity generator.

Language: C++ - Size: 4.13 MB - Last synced at: 1 day ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

rpm2003rpm/stg2veriloga

converts a stg (.g file generated by workcraft) to a verilogA model

Language: Python - Size: 141 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

rnibhriain/digital-logic-design

Digital logic :triangular_ruler: assignments for module: CSU11026

Language: Verilog - Size: 6.84 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

ZhefeiGong/TongjiWork_slep

A steerable localization environmental perception car

Language: Verilog - Size: 20.3 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

zahi1/Digital-Electronics

Digital Electronics repo includes Boolean algebra and logic circuit design, covering topics such as gates, combinational and sequential circuits. It will help you learn logical circuit design principles, analyze circuits using automated tools, and delve into VHDL coding for the design and implementation of digital circuits on FPGA devices.

Size: 2.42 MB - Last synced at: 2 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

stefanodangelo/academicprojects

This repository contains all the academic projects made during the studies for the Bachelor's Degree in Engineering of Computing Systems and for the M.Sc. in Data Science.

Language: Jupyter Notebook - Size: 146 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

ejdotp/SemThree_ITER

Code collective of my 3rd Semester at ITER

Language: HTML - Size: 23.6 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

hsr-22/EE224_CPU-IITB

Course Project for EE224 (Digital Systems) offered in Autumn 2023

Language: VHDL - Size: 123 MB - Last synced at: 10 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

yigittuncer07/processor 📦

A processor design using logism and verilog.

Language: C - Size: 806 KB - Last synced at: 11 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Abduullaahh/Computer-Science-Academia

This repository contains data related to BS Computer Science

Language: C++ - Size: 791 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

FasiulAbedinKhan/EEE283-Theory-Project-PlantMonitoringSystem

In our EEE283 Project, we're creating an automatic plant monitoring and irrigation system. Utilizing arithmetic, sequential, and combinational circuits.

Size: 1.02 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

FasiulAbedinKhan/EEE283-Lab-Project-ElectronicVotingMachine

We have developed an Electronic Voting Machine designed to tally the votes of 60 individuals. In this setup, there are six candidates vying for positions.

Size: 7.57 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

priscia99/digital-logic-design-project

This project aims to create a network of logic gates that implements a simplified version of the standard algorithm for the histogram equalization method of an image, by recalibrating the contrast of an image when the range of intensity values is very close together.

Language: VHDL - Size: 7.45 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Ammar-Bin-Amir/RTL_Design

RTL (Register Transfer Level) Designing

Language: Verilog - Size: 2.73 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CrystaS15/Computer-Logic-Design-I

Logic gates, simplification of Boolean functions, design and testing of combinational and sequential circuits including code converters, multiplexers, adders, and synchronous counters. For non-electrical and non-computer engineering majors only.

Size: 117 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

alumpish/DLD-Lab-Projects

Projects of the digital logic design lab (Fall01) at the University of Tehran.

Language: Verilog - Size: 5 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

BRAINIAC2677/CSE-206-Digital-Logic-Design

Contains the logisim designs of the lab works of CSE206.

Size: 8.8 MB - Last synced at: about 2 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

theavidstallion/university-projects

This repository is dedicated to store university projects I have done.

Language: C++ - Size: 3.47 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

wecacuee/ECE275-F22-Sequential-Logic

Course website for ECE275: Sequential logic systems, Fall 2021 for the University of Maine

Language: Dockerfile - Size: 91.3 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

MuhammadAbdullahNaeem1/DLD_Stack

A Digital Logic Design based project working the implementation of Stack Data Structure using all the gates including AND,OR,XOR,XNOR and MUX.Works on LogicWorks 5

Size: 23.4 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

TheViking733n/Tic-Tac-Toe_Verilog

This is a simple two player Tic-Tac-Toe game made using Digital Logic Simulator

Size: 28.3 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

zyn10/Digital_Logic_Design

Digital Logic Design Clutter

Size: 25.8 MB - Last synced at: 2 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

nishatrhythm/Digital-Logic-Design-Lab 📦

Digital Logic Design (.circ) related files can be found here. You must run those files in Logisim software.

Size: 45.9 KB - Last synced at: about 2 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

ashna-verma/Quine-McKlusky Fork of mariyam-siddiqui/Quine-McKlusky

Karnaugh maps solver is a web app that takes the truth table of a function as input, transposes it onto the respective Karnaugh map and finds the minimum forms SOP and POS according to the visual resolution method by Maurice Karnaugh, American physicist and mathematician. Implementation of the Quine - McKlusky algorithm in C++

Language: Python - Size: 9.45 MB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0