Topic: "digital-logic-design-lab"
Amey-Thakur/DIGITAL-LOGIC-DESIGN-AND-ANALYSIS-AND-DIGITAL-SYSTEM-LAB
CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] <Semester III>
Size: 185 MB - Last synced at: 6 days ago - Pushed at: over 1 year ago - Stars: 10 - Forks: 1
SM2A/University_Projects
🎓💻All of my projects at University of Tehran
Size: 38.1 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 8 - Forks: 0
PashaBarahimi/Digital-Logic-Design-Lab-Experiments
Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.
Language: Verilog - Size: 9.9 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 2
burhanahmed1/BitCalculator
BitCalculator is used for bitwise arithematic operations like addition, subtraction, multiplication etc.
Size: 6.77 MB - Last synced at: 4 months ago - Pushed at: 12 months ago - Stars: 1 - Forks: 0
alirezahabib/sut-dldl
Digital Logic Design Lab, Sharif University of Technology
Language: TeX - Size: 27.8 MB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0
MisaghM/Digital-Logic-Design-Lab-Experiments Fork of PashaBarahimi/Digital-Logic-Design-Lab-Experiments
Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.
Size: 9.89 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0
FasiulAbedinKhan/EEE283-Lab-Project-ElectronicVotingMachine
We have developed an Electronic Voting Machine designed to tally the votes of 60 individuals. In this setup, there are six candidates vying for positions.
Size: 7.57 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
Al-Shafi-Github/7-Segment-Display-Using-Different-Gates
This Project is about 7 segment display of an ID using Different Gates and Multiplexers,Decoders
Size: 39.1 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
saifmohammednipun/dgital-logic-design-lab
This repository contains the lab works of Digital Logic Design (DLD) Course.
Size: 3.14 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
Shehab-Naga/VHDL-Exercises
My work for the laboratory exercises provided by intel FPGAcademy (Digital Logic) during my internship at PyramidTech in Summer 2022.
Language: VHDL - Size: 1.44 MB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0
EarthAkkharawat/Vending-machine
Built vending machine circuit using sequential logic design
Size: 299 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
