Topic: "fpga"
openwall/john
John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs
Language: C - Size: 127 MB - Last synced at: 10 days ago - Pushed at: 11 days ago - Stars: 11,389 - Forks: 2,246
PaddlePaddle/Paddle-Lite
PaddlePaddle High Performance Deep Learning Inference Engine for Mobile and Edge (飞桨高性能深度学习端侧推理引擎）
Language: C++ - Size: 314 MB - Last synced at: 3 days ago - Pushed at: 16 days ago - Stars: 7,097 - Forks: 1,619
logisim-evolution/logisim-evolution
Digital logic design tool and simulator
Language: Java - Size: 109 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 5,793 - Forks: 733
open-sdr/openwifi
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
Language: C - Size: 24.4 MB - Last synced at: 18 days ago - Pushed at: 21 days ago - Stars: 4,160 - Forks: 703
LeiWang1999/FPGA
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
Size: 58.6 KB - Last synced at: 8 months ago - Pushed at: about 3 years ago - Stars: 3,905 - Forks: 658
enjoy-digital/litex
Build your hardware, easily!
Language: C - Size: 16.9 MB - Last synced at: 4 days ago - Pushed at: 5 days ago - Stars: 3,346 - Forks: 623
SpinalHDL/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
Language: Assembly - Size: 12.7 MB - Last synced at: 10 days ago - Pushed at: about 1 month ago - Stars: 2,775 - Forks: 446
openhwgroup/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Language: Assembly - Size: 139 MB - Last synced at: 10 days ago - Pushed at: 12 days ago - Stars: 2,487 - Forks: 772
darklife/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Language: Verilog - Size: 3.94 MB - Last synced at: 18 days ago - Pushed at: 18 days ago - Stars: 2,319 - Forks: 304
jbush001/NyuziProcessor
GPGPU microprocessor architecture
Language: C - Size: 31.4 MB - Last synced at: 9 days ago - Pushed at: 7 months ago - Stars: 2,082 - Forks: 360
GlasgowEmbedded/glasgow
Scots Army Knife for electronics
Language: Python - Size: 44.3 MB - Last synced at: 3 days ago - Pushed at: 4 days ago - Stars: 1,999 - Forks: 205
corundum/corundum
Open source FPGA-based NIC and platform for in-network compute
Language: Verilog - Size: 19.5 MB - Last synced at: 9 days ago - Pushed at: 11 months ago - Stars: 1,891 - Forks: 455
SpinalHDL/SpinalHDL
Scala based HDL
Language: Scala - Size: 81.3 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 1,793 - Forks: 346
FPGAwars/icestudio
:snowflake: Visual editor for open FPGA boards
Language: JavaScript - Size: 120 MB - Last synced at: 17 days ago - Pushed at: about 2 months ago - Stars: 1,778 - Forks: 254
stnolting/neorv32
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Language: VHDL - Size: 226 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 1,774 - Forks: 263
amaranth-lang/amaranth
A modern hardware definition language and toolchain based on Python
Language: Python - Size: 3.75 MB - Last synced at: 18 days ago - Pushed at: 23 days ago - Stars: 1,694 - Forks: 178
analogdevicesinc/hdl
HDL libraries and projects
Language: Verilog - Size: 86.8 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 1,659 - Forks: 1,564
pConst/basic_verilog
Must-have verilog systemverilog modules
Language: Verilog - Size: 54.2 MB - Last synced at: 8 months ago - Pushed at: 11 months ago - Stars: 1,627 - Forks: 376
olofk/serv
SERV - The SErial RISC-V CPU
Language: Verilog - Size: 12.5 MB - Last synced at: 9 days ago - Pushed at: 22 days ago - Stars: 1,589 - Forks: 219
clash-lang/clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
Language: Haskell - Size: 19.7 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1,501 - Forks: 161
fastmachinelearning/hls4ml
Machine learning on FPGAs using HLS
Language: C++ - Size: 257 MB - Last synced at: 3 days ago - Pushed at: 4 days ago - Stars: 1,490 - Forks: 455
riscv-mcu/e203_hbirdv2
The Ultra-Low Power RISC-V Core
Language: Verilog - Size: 59.5 MB - Last synced at: 3 months ago - Pushed at: 8 months ago - Stars: 1,442 - Forks: 362
ultraembedded/riscv
RISC-V CPU Core (RV32IM)
Language: Verilog - Size: 5.27 MB - Last synced at: 3 months ago - Pushed at: over 3 years ago - Stars: 1,398 - Forks: 251
Xilinx/Vitis-Tutorials
Vitis In-Depth Tutorials
Language: C - Size: 780 MB - Last synced at: about 23 hours ago - Pushed at: about 24 hours ago - Stars: 1,390 - Forks: 568
sylefeb/Silice
Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.
Language: C++ - Size: 53 MB - Last synced at: about 2 months ago - Pushed at: 2 months ago - Stars: 1,354 - Forks: 82
trabucayre/openFPGALoader
Universal utility for programming FPGA
Language: C++ - Size: 7.18 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 1,337 - Forks: 290
Xilinx/brevitas
Brevitas: neural network quantization in PyTorch
Language: Python - Size: 65 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1,327 - Forks: 216
platformio/platformio-vscode-ide
PlatformIO IDE for VSCode: The next generation integrated development environment for IoT
Language: JavaScript - Size: 1.96 MB - Last synced at: 17 days ago - Pushed at: 5 months ago - Stars: 1,295 - Forks: 214
olofk/fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
Language: Python - Size: 2.48 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1,294 - Forks: 258
ZipCPU/zipcpu
A small, light weight, RISC CPU soft core
Language: Verilog - Size: 256 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 1,289 - Forks: 154
pulp-platform/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Language: SystemVerilog - Size: 9.12 MB - Last synced at: 18 days ago - Pushed at: 18 days ago - Stars: 1,279 - Forks: 290
doonny/PipeCNN
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
Language: C - Size: 3.7 MB - Last synced at: 7 months ago - Pushed at: over 3 years ago - Stars: 1,252 - Forks: 369
cariboulabs/cariboulite
CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
Language: C - Size: 234 MB - Last synced at: 10 days ago - Pushed at: 4 months ago - Stars: 1,211 - Forks: 122
hdl-util/hdmi
Send video/audio over HDMI on an FPGA
Language: SystemVerilog - Size: 4.13 MB - Last synced at: 2 days ago - Pushed at: over 1 year ago - Stars: 1,166 - Forks: 127
verilog-to-routing/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Language: C++ - Size: 319 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 1,103 - Forks: 415
hukenovs/dsp-theory
Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc.
Language: Jupyter Notebook - Size: 29.4 MB - Last synced at: 15 days ago - Pushed at: 9 months ago - Stars: 1,092 - Forks: 187
EttusResearch/uhd
The USRP™ Hardware Driver Repository
Language: Verilog - Size: 140 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 1,070 - Forks: 688
oneapi-src/oneAPI-samples
Samples for Intel® oneAPI Toolkits
Language: C++ - Size: 411 MB - Last synced at: 2 days ago - Pushed at: 3 days ago - Stars: 1,037 - Forks: 727
greatscottgadgets/luna
Amaranth HDL framework for monitoring, hacking, and developing USB devices
Language: Python - Size: 14.1 MB - Last synced at: 2 days ago - Pushed at: 3 months ago - Stars: 1,027 - Forks: 171
ultraembedded/biriscv
32-bit Superscalar RISC-V CPU
Language: Verilog - Size: 2.98 MB - Last synced at: 14 days ago - Pushed at: over 3 years ago - Stars: 1,021 - Forks: 171
siliconcompiler/siliconcompiler
Modular hardware build system
Language: Python - Size: 336 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 1,000 - Forks: 103
circuitvalley/USB_C_Industrial_Camera_FPGA_USB3
Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
Language: Verilog - Size: 57.4 MB - Last synced at: 19 days ago - Pushed at: over 1 year ago - Stars: 969 - Forks: 186
eugene-tarassov/vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Language: Tcl - Size: 36.1 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 933 - Forks: 209
firesim/firesim
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
Language: Scala - Size: 60.5 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 931 - Forks: 238
lnis-uofu/OpenFPGA
An Open-source FPGA IP Generator
Language: Verilog - Size: 89.2 MB - Last synced at: 3 days ago - Pushed at: 4 days ago - Stars: 915 - Forks: 170
riscvarchive/riscv-cores-list 📦
RISC-V Cores, SoC platforms and SoCs
Size: 194 KB - Last synced at: about 2 months ago - Pushed at: about 4 years ago - Stars: 871 - Forks: 210
chipsalliance/Cores-VeeR-EH1
VeeR EH1 core
Language: SystemVerilog - Size: 17.6 MB - Last synced at: about 2 months ago - Pushed at: about 2 years ago - Stars: 870 - Forks: 227
FPGAwars/apio
:seedling: Open source ecosystem for open FPGA boards
Language: Verilog - Size: 147 MB - Last synced at: 5 days ago - Pushed at: 6 days ago - Stars: 849 - Forks: 143
Xilinx/finn
Dataflow compiler for QNN inference on FPGAs
Language: Python - Size: 85.4 MB - Last synced at: 3 days ago - Pushed at: 4 days ago - Stars: 828 - Forks: 260
splinedrive/kianRiscV
RISC-V Linux SoC, marchID: 0x2b
Language: Assembly - Size: 198 MB - Last synced at: about 2 months ago - Pushed at: 3 months ago - Stars: 816 - Forks: 58
fpgasystems/fpga-network-stack
Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
Language: C++ - Size: 18.6 MB - Last synced at: about 2 months ago - Pushed at: 3 months ago - Stars: 807 - Forks: 283
f4pga/prjxray
Documenting the Xilinx 7-series bit-stream format.
Language: Python - Size: 6.51 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 804 - Forks: 156
Obijuan/open-fpga-verilog-tutorial
Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
Language: Verilog - Size: 36.6 MB - Last synced at: 14 days ago - Pushed at: about 5 years ago - Stars: 804 - Forks: 199
Cr4sh/s6_pcie_microblaze
PCI Express DIY hacking toolkit for Xilinx SP605. This repository is also home of Hyper-V Backdoor and Boot Backdoor, check readme for links and info
Language: C - Size: 38.4 MB - Last synced at: 15 days ago - Pushed at: about 1 year ago - Stars: 795 - Forks: 162
romeric/Fastor
A lightweight high performance tensor algebra framework for modern C++
Language: C++ - Size: 3.2 MB - Last synced at: about 1 month ago - Pushed at: about 1 year ago - Stars: 780 - Forks: 77
VUnit/vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
Language: VHDL - Size: 14 MB - Last synced at: 3 days ago - Pushed at: 27 days ago - Stars: 775 - Forks: 276
open-sdr/openwifi-hw
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
Language: Verilog - Size: 484 MB - Last synced at: 9 days ago - Pushed at: about 1 month ago - Stars: 757 - Forks: 258
ultraembedded/cores
Various HDL (Verilog) IP Cores
Language: Verilog - Size: 211 KB - Last synced at: 3 months ago - Pushed at: almost 4 years ago - Stars: 745 - Forks: 218
WangXuan95/FPGA-USB-Device
An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed) device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。
Language: Verilog - Size: 494 KB - Last synced at: about 2 months ago - Pushed at: 6 months ago - Stars: 722 - Forks: 120
xupsh/pp4fpgas-cn
中文版 Parallel Programming for FPGAs
Language: CSS - Size: 37.6 MB - Last synced at: 2 months ago - Pushed at: 10 months ago - Stars: 719 - Forks: 159
PrincetonUniversity/openpiton
The OpenPiton Platform
Language: Assembly - Size: 88.9 MB - Last synced at: 15 days ago - Pushed at: 18 days ago - Stars: 705 - Forks: 237
konosubakonoakua/FPGA_MCU_Debugger_Collections
各种LInk大合集
Language: C - Size: 212 MB - Last synced at: about 2 months ago - Pushed at: 2 months ago - Stars: 704 - Forks: 299
nickg/nvc
VHDL compiler and simulator
Language: C - Size: 25.2 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 696 - Forks: 89
olofk/edalize
An abstraction library for interfacing EDA tools
Language: Python - Size: 1.08 MB - Last synced at: 17 days ago - Pushed at: about 1 month ago - Stars: 687 - Forks: 201
m-labs/nmigen
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
Language: Python - Size: 1.3 MB - Last synced at: 1 day ago - Pushed at: over 3 years ago - Stars: 672 - Forks: 59
emsec/hal
HAL – The Hardware Analyzer
Language: C++ - Size: 3.11 GB - Last synced at: 9 days ago - Pushed at: 10 days ago - Stars: 668 - Forks: 84
JulianKemmerer/PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Language: VHDL - Size: 76.4 MB - Last synced at: 16 days ago - Pushed at: 18 days ago - Stars: 653 - Forks: 51
projf/projf-explore
Project F brings FPGAs to life with exciting open-source designs you can build on.
Language: SystemVerilog - Size: 3.05 MB - Last synced at: about 2 months ago - Pushed at: 5 months ago - Stars: 637 - Forks: 56
WalkerLau/Accelerating-CNN-with-FPGA
This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.
Language: C++ - Size: 103 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 624 - Forks: 174
TerosTechnology/vscode-terosHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Language: VHDL - Size: 150 MB - Last synced at: 3 days ago - Pushed at: 2 months ago - Stars: 619 - Forks: 53
trivialmips/nontrivial-mips
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
Language: SystemVerilog - Size: 20.4 MB - Last synced at: about 11 hours ago - Pushed at: almost 5 years ago - Stars: 602 - Forks: 103
Xilinx/XRT
Run Time for AIE and FPGA based platforms
Language: C++ - Size: 124 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 598 - Forks: 490
VLSI-EDA/PoC
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
Language: VHDL - Size: 4.96 MB - Last synced at: about 2 months ago - Pushed at: over 4 years ago - Stars: 577 - Forks: 103
google/qkeras
QKeras: a quantization deep learning library for Tensorflow Keras
Language: Python - Size: 1.53 MB - Last synced at: 5 days ago - Pushed at: 2 months ago - Stars: 567 - Forks: 108
WangXuan95/BSV_Tutorial_cn
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
Language: Bluespec - Size: 31.1 MB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 566 - Forks: 44
seldridge/verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
Language: Verilog - Size: 72.3 KB - Last synced at: 2 months ago - Pushed at: about 7 years ago - Stars: 564 - Forks: 140
zssloth/Embedded-Neural-Network
collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning
Size: 52.7 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 547 - Forks: 121
ZipCPU/wb2axip
Bus bridges and other odds and ends
Language: Verilog - Size: 8.78 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 544 - Forks: 110
spcl/dace
DaCe - Data Centric Parallel Programming
Language: Python - Size: 66.8 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 535 - Forks: 139
dtysky/FPGA-Imaging-Library
An open source library for image processing on FPGA.
Language: Verilog - Size: 59.2 MB - Last synced at: over 1 year ago - Pushed at: almost 10 years ago - Stars: 489 - Forks: 211
platformio/platformio-atom-ide 📦
PlatformIO IDE for Atom: The next generation integrated development environment for IoT
Language: JavaScript - Size: 1.12 MB - Last synced at: 5 months ago - Pushed at: over 4 years ago - Stars: 476 - Forks: 71
jofrfu/tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Language: VHDL - Size: 1.42 MB - Last synced at: 12 days ago - Pushed at: over 6 years ago - Stars: 465 - Forks: 66
WangXuan95/FPGA-FOC
FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
Language: Verilog - Size: 666 KB - Last synced at: 12 months ago - Pushed at: over 1 year ago - Stars: 459 - Forks: 148
fabriziotappero/ip-cores
A huge collection of VHDL/Verilog open-source IP cores scraped from the web
Size: 649 MB - Last synced at: about 2 months ago - Pushed at: over 2 years ago - Stars: 459 - Forks: 138
jks-prv/Beagle_SDR_GPS
KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS
Language: C++ - Size: 269 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 452 - Forks: 155
vmware-archive/cascade 📦
A Just-In-Time Compiler for Verilog from VMware Research
Language: C++ - Size: 19.2 MB - Last synced at: 25 days ago - Pushed at: almost 4 years ago - Stars: 444 - Forks: 44
triSYCL/triSYCL
Generic system-wide modern C++ for heterogeneous platforms with SYCL from Khronos Group
Language: C++ - Size: 382 MB - Last synced at: 7 days ago - Pushed at: 7 months ago - Stars: 443 - Forks: 98
cheyao/icepi-zero
ECP5 Development Board in the Raspberry Pi Zero form
Language: HTML - Size: 18.4 MB - Last synced at: 1 day ago - Pushed at: 2 days ago - Stars: 442 - Forks: 12
tommythorn/Reduceron
FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.
Language: Haskell - Size: 8.62 MB - Last synced at: 15 days ago - Pushed at: about 1 month ago - Stars: 434 - Forks: 33
circuitvalley/mipi_csi_receiver_FPGA
MIPI CSI-2 Camera Sensor Receiver verilog HDL implementation For any generic FPGA. Tested with IMX219 on Lattice MachXO3LF. 2Gbps UVC Video Stream Over USB 3.0 with Cypress FX3. This is now Legacy Version!
Language: C - Size: 29.4 MB - Last synced at: 13 days ago - Pushed at: almost 3 years ago - Stars: 418 - Forks: 127
rprinz08/hBPF
hBPF = eBPF in hardware
Language: Python - Size: 8.39 MB - Last synced at: 5 days ago - Pushed at: over 2 years ago - Stars: 414 - Forks: 24
f32c/f32c
A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
Language: C - Size: 11.7 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 413 - Forks: 105
tillitis/tillitis-key1
FPGA verilog and firmware for TKey, the flexible and open USB security key 🔑
Language: C - Size: 22.4 MB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 409 - Forks: 28
gu0y1/picture2pixel
A Python library for converting images into FPGA-displayable pixel art.
Language: Python - Size: 53.7 KB - Last synced at: about 1 month ago - Pushed at: 5 months ago - Stars: 399 - Forks: 12
WangXuan95/USTC-RVSoC
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
Language: SystemVerilog - Size: 62.2 MB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 398 - Forks: 79
agg23/openfpga-SNES
SNES for the Analogue Pocket
Language: VHDL - Size: 6.58 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 397 - Forks: 16
bperez77/xilinx_axidma
A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
Language: C - Size: 271 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 395 - Forks: 206
rggen/rggen
Code generation tool for control and status registers
Language: Ruby - Size: 511 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 387 - Forks: 46
slaclab/surf
A huge VHDL library for FPGA and digital ASIC development
Language: VHDL - Size: 169 MB - Last synced at: 3 days ago - Pushed at: 4 days ago - Stars: 384 - Forks: 71
nand2mario/nestang
NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards
Language: Verilog - Size: 9.84 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 383 - Forks: 42
