open-sdr/openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Language: C - Size: 24 MB - Last synced at: 4 days ago - Pushed at: 5 days ago - Stars: 4,116 - Forks: 697

f4pga/prjxray

Documenting the Xilinx 7-series bit-stream format.

Language: Python - Size: 6.51 MB - Last synced at: about 20 hours ago - Pushed at: 4 days ago - Stars: 796 - Forks: 156

f4pga/f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Language: Jupyter Notebook - Size: 9.52 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 281 - Forks: 113

fpgasystems/Coyote

Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.

Language: SystemVerilog - Size: 593 MB - Last synced at: about 16 hours ago - Pushed at: 15 days ago - Stars: 248 - Forks: 77

ingonyama-zk/blaze

blaze is a Rust library for ZK acceleration on Xilinx FPGAs.

Language: Rust - Size: 2.25 MB - Last synced at: 11 days ago - Pushed at: 6 months ago - Stars: 145 - Forks: 19

ultraembedded/openlogicbit

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

Language: Verilog - Size: 606 KB - Last synced at: about 2 months ago - Pushed at: almost 4 years ago - Stars: 133 - Forks: 18

triSYCL/sycl

SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM

Language: C++ - Size: 1.37 GB - Last synced at: 10 days ago - Pushed at: 6 months ago - Stars: 116 - Forks: 21

derekmulcahy/xvcpi

Xilinx Virtual Cable Server for Raspberry Pi

Language: C - Size: 290 KB - Last synced at: 2 days ago - Pushed at: about 3 years ago - Stars: 113 - Forks: 28

ultraembedded/core_ft60x_axi

FTDI FT600 SuperSpeed USB3.0 to AXI bus master

Language: C++ - Size: 4.29 MB - Last synced at: 16 days ago - Pushed at: almost 5 years ago - Stars: 94 - Forks: 27

chipsalliance/yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.

Language: Verilog - Size: 4.57 MB - Last synced at: 13 days ago - Pushed at: 11 months ago - Stars: 83 - Forks: 47

ultraembedded/core_dvi_framebuffer

Minimal DVI / HDMI Framebuffer

Language: Verilog - Size: 77.1 KB - Last synced at: about 2 months ago - Pushed at: over 4 years ago - Stars: 79 - Forks: 12

f4pga/prjuray

Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

Language: SystemVerilog - Size: 1.37 MB - Last synced at: about 1 year ago - Pushed at: about 3 years ago - Stars: 66 - Forks: 12

f4pga/prjxray-db

Project X-Ray Database: XC7 Series

Language: Shell - Size: 62.5 MB - Last synced at: 5 months ago - Pushed at: over 3 years ago - Stars: 63 - Forks: 32

ingonyama-zk/open-binius

building blocks for accelerating ZK proofs over binary fields

Language: Verilog - Size: 9.6 MB - Last synced at: 13 days ago - Pushed at: 9 months ago - Stars: 44 - Forks: 3

pontazaricardo/Verilog_Calculator_Matrix_Multiplication

This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.

Language: Verilog - Size: 3.73 MB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 34 - Forks: 8

stevenbell/csirx

Open-source CSI-2 receiver for Xilinx UltraScale parts

Language: Verilog - Size: 11.6 MB - Last synced at: over 1 year ago - Pushed at: almost 6 years ago - Stars: 32 - Forks: 13

diogofferreira/fpga-miner

:moneybag: A simplified version of an FPGA bitcoin miner :moneybag:

Language: VHDL - Size: 344 MB - Last synced at: about 2 years ago - Pushed at: almost 6 years ago - Stars: 32 - Forks: 23

fredrequin/verilator_xilinx

Re-coded Xilinx primitives for Verilator use

Language: Verilog - Size: 151 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 30 - Forks: 2

sailordiary/computer-systems-ucas

中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session

Language: Verilog - Size: 52.4 MB - Last synced at: over 1 year ago - Pushed at: almost 8 years ago - Stars: 27 - Forks: 8

geraked/verilog-rle

Verilog Implementation of Run Length Encoding for RGB Image Compression

Language: Verilog - Size: 11.6 MB - Last synced at: 4 days ago - Pushed at: almost 4 years ago - Stars: 25 - Forks: 4

hex-five/multizone-fpga Fork of sifive/freedom

This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 SoC is Hex Five's official reference platform for its MultiZone Security Trusted Execution Environment and MultiZone Security Trusted Firmware. The X300 is an enhanced secure version of the - now archived - SiFive's Freedom E300 Platform built around the RISC-V Rocket chip originally developed at U.C. Berkeley.

Language: Scala - Size: 212 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 24 - Forks: 5

Wissance/QuickSPI

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

Language: Verilog - Size: 127 KB - Last synced at: 19 days ago - Pushed at: over 7 years ago - Stars: 22 - Forks: 7

olivier-le-sage/camera-filters

Colorspace conversion, gamma correction, and more -- all integrated within a MIPI-to-HDMI pipeline in FPGA.

Language: VHDL - Size: 64.4 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 21 - Forks: 15

sarthak268/Embedded_Logic_and_Design

This repository contains all labs done as a part of the Embedded Logic and Design course.

Size: 14.7 MB - Last synced at: 12 months ago - Pushed at: almost 7 years ago - Stars: 21 - Forks: 2

hex-five/multizone-iot-sdk

MultiZone® Trusted Firmware is the quick and safe way to build secure IoT applications with any RISC-V processor. It provides secure access to commercial and private IoT clouds, real-time monitoring, secure boot, and remote firmware updates. The built-in Trusted Execution Environment provides hardware-enforced separation ...

Language: C - Size: 8.31 MB - Last synced at: 2 days ago - Pushed at: about 1 year ago - Stars: 19 - Forks: 1

splAcharya/DigitalOscilloscope_Zynq7000Soc

A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.

Size: 71.2 MB - Last synced at: 5 months ago - Pushed at: over 4 years ago - Stars: 18 - Forks: 4

SalvatoreBarone/CNN-VHDL

A library of VHDL components for Neural Networks

Language: C++ - Size: 32.8 MB - Last synced at: 3 days ago - Pushed at: over 3 years ago - Stars: 17 - Forks: 3

charkster/spi_slave_verilog

SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs

Language: Verilog - Size: 30.3 KB - Last synced at: about 1 month ago - Pushed at: over 5 years ago - Stars: 15 - Forks: 11

Thraetaona/Innervator

Innervator: Hardware Acceleration for Neural Networks

Language: VHDL - Size: 2.86 MB - Last synced at: 11 days ago - Pushed at: 9 months ago - Stars: 14 - Forks: 1

KarenOk/SAP-1-Computer

Design and Implementation of a Simple-As-Possible 1 (SAP-1) Computer using an FPGA and VHDL.

Language: VHDL - Size: 2.25 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 14 - Forks: 8

mcagriaksoy/VHDL-FPGA-LAB_PROJECTS

My Lab Assigments from Bachelor Degree, This repo includes the projects for digital systems II Lecture (EEM334)

Language: VHDL - Size: 575 KB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 14 - Forks: 2

theshadowx/keyboard-ip

PS/2 Keyboard IP written in VHDL for Xilinx FPGA

Language: VHDL - Size: 174 KB - Last synced at: about 2 years ago - Pushed at: almost 10 years ago - Stars: 14 - Forks: 2

mcedrdiego/Kria_yolov3_ppe

Xilinx Kria KV260 Real-time PPE detection

Language: C++ - Size: 116 MB - Last synced at: 2 days ago - Pushed at: about 2 years ago - Stars: 13 - Forks: 0

AnyDSL/anyhls

High-Level Synthesis with Partial Evaluation

Language: CMake - Size: 81.1 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 11 - Forks: 1

mattuna15/merlin

Learn how to create your own 32-bit system from scratch.

Language: Assembly - Size: 19 MB - Last synced at: about 1 year ago - Pushed at: about 3 years ago - Stars: 11 - Forks: 2

Wissance/2DImageProcessing

2d Images processing system with FPGA (Zynq 7k) from two dragster linescanner (DR-2k-7)

Language: VHDL - Size: 36.9 MB - Last synced at: 19 days ago - Pushed at: over 7 years ago - Stars: 11 - Forks: 5

WualFabre/FPGA-Verilog

Practices related to the fundamental level of the programming language Verilog.

Language: Verilog - Size: 5.35 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 10 - Forks: 1

jmduarte/HLS_hls4ml_Tutorial

HLS & hls4ml Tutorial

Language: Jupyter Notebook - Size: 16.9 MB - Last synced at: 6 days ago - Pushed at: over 4 years ago - Stars: 10 - Forks: 6

Wissance/ImageCaptureSystem

A Xilinx IP Core and App for line scanner image capture and store

Language: VHDL - Size: 43.6 MB - Last synced at: 19 days ago - Pushed at: over 7 years ago - Stars: 10 - Forks: 6

Yourigh/Rotary-encoder-VHDL-design

VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.

Language: VHDL - Size: 25.4 KB - Last synced at: almost 2 years ago - Pushed at: about 8 years ago - Stars: 10 - Forks: 2

AnyDSL/flower

A Comprehensive Dataflow Compiler for High-Level Synthesis

Language: CMake - Size: 3.61 MB - Last synced at: 5 days ago - Pushed at: 6 days ago - Stars: 9 - Forks: 3

siorpaes/SimpleSoC

Very simple Cortex-M1 SoC design based on ARM DesignStart

Language: C - Size: 206 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 8 - Forks: 2

islandcontroller/ArduinoXVC

Xilinx Virtual Cable (XVC) Server implementation for use with an Arduino UNO/Leonardo

Language: C++ - Size: 139 KB - Last synced at: 9 days ago - Pushed at: over 4 years ago - Stars: 8 - Forks: 2

ilyajob05/verilog_modules

verilog modules

Language: Verilog - Size: 27.3 KB - Last synced at: almost 2 years ago - Pushed at: almost 5 years ago - Stars: 8 - Forks: 2

santifs/ultrasonic-sensor

Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.

Language: VHDL - Size: 6.83 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 8 - Forks: 2

ChamanAgrawal/CS220

This repository contains lab assignments done in the course CS220: Computer Organization at IIT Kanpur

Language: HTML - Size: 4.42 MB - Last synced at: almost 2 years ago - Pushed at: over 5 years ago - Stars: 8 - Forks: 0

simoneruffini/NORM

Framework for emulation of non volatile memory using off-the-shelf FPGAs

Language: VHDL - Size: 27.2 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 7 - Forks: 1

ViktorSlavkovic/FPGA_Tetris

FPGA Tetris written in Verilog

Language: Verilog - Size: 75.2 KB - Last synced at: about 1 year ago - Pushed at: almost 7 years ago - Stars: 7 - Forks: 2

DylanVanAssche/digitale-synthese

DSSS Wireless transmit-receive system in VHDL

Language: VHDL - Size: 14.6 MB - Last synced at: over 1 year ago - Pushed at: over 7 years ago - Stars: 7 - Forks: 2

luminoso/cr-countones

Xilinx Vivado demo project with design, IP, SDK interaction, VGA, finite state machine and outputs

Language: VHDL - Size: 25.6 MB - Last synced at: 6 months ago - Pushed at: over 7 years ago - Stars: 7 - Forks: 1

10x-Engineers/Infinite-ISP_FPGABinaries

Infinite-ISP Image Signal Processing Pipeline FPGA Binaries for XCK26 Zynq® UltraScale+™ MPSoC present on Xilinx® Kria™ KV260 Vision AI Starter Kit and Efinix® Titanium Ti180 J484 Development Kit

Language: Python - Size: 52.4 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 6 - Forks: 4

Multimedia-Processing/Digital-Logic-Design

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

Language: Verilog - Size: 181 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 6 - Forks: 2

charkster/cmod_a7_spi_sram

SPI slave to External SRAM interface for Cmod A7

Language: SystemVerilog - Size: 13.7 KB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 6 - Forks: 1

neeraj1397/Performance-Analysis-of-Parallel-Prefix-Adders-Using-Zynq-7000-APSoC

Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.

Language: Verilog - Size: 653 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 6 - Forks: 2

IzyaSoft/EasyHDLLib

A coocbook of HDL (primarily Verilog) modules

Language: Verilog - Size: 315 KB - Last synced at: 17 days ago - Pushed at: almost 8 years ago - Stars: 6 - Forks: 0

hossein1387/ZYBO

This repository contains my Linux builds and projects for ZYBO Zynq dev board

Language: Tcl - Size: 14.6 MB - Last synced at: about 2 years ago - Pushed at: about 8 years ago - Stars: 6 - Forks: 5

bsc-pm-ompss-at-fpga/ait

The Accelerator Integration Tool (AIT) automatically integrates OmpSs@FPGA accelerators into FPGA designs using different vendor backends

Language: Tcl - Size: 10.5 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 5 - Forks: 2

sajadh76/UART-Protocol

Discover the Xilinx Spartan-6 FPGA implementation featuring a UART protocol and Bubble Sort algorithm

Language: VHDL - Size: 8.79 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 5 - Forks: 0

zpekic/Sys0800

VHDL implementation of vintage TMS0800 calculator chip

Language: VHDL - Size: 7.99 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 5 - Forks: 3

ashvnv/FPGA-Ping-Pong-game

Simple Ping Pong game on Xilinx Spartan 3E

Language: HTML - Size: 13.9 MB - Last synced at: about 1 month ago - Pushed at: almost 3 years ago - Stars: 5 - Forks: 2

Kampi/TinyAVR

VHDL design of an AVR8 CPU.

Language: VHDL - Size: 1.63 MB - Last synced at: 7 days ago - Pushed at: over 3 years ago - Stars: 5 - Forks: 0

kuoyaoming93/sem-ip_pynq

SEM (Soft Error Mitigation) IP adapted for PYNQ-Z2

Language: Tcl - Size: 17.8 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 5 - Forks: 1

lazyoracle/vhdl-processor

An 8-bit processor in VHDL based on a simple instruction set

Language: VHDL - Size: 209 KB - Last synced at: 10 months ago - Pushed at: about 6 years ago - Stars: 5 - Forks: 0

jofrfu/HAW-V

Fork of a RISC-V compliant CPU, which originated in a project at the HAW Hamburg

Language: VHDL - Size: 31.9 MB - Last synced at: 14 days ago - Pushed at: about 6 years ago - Stars: 5 - Forks: 3

mwil/wifire

FPGA and firmware images for the USRP2 to operate as a Wireless Firewall (WiFire)

Language: C++ - Size: 4.36 MB - Last synced at: about 2 years ago - Pushed at: almost 8 years ago - Stars: 5 - Forks: 2

JeffDeCola/control-fpga-via-raspi-and-webserver

Control a FPGA via a Raspberry Pi and a Webserver.

Language: JavaScript - Size: 16.4 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 4 - Forks: 0

aproposorg/KV260-PYNQ-tutorial

Simple PYNQ KV260 tutorial: Porting C-based design into FPGA via Xilinx HLS

Language: Jupyter Notebook - Size: 106 MB - Last synced at: 12 months ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 3

NicolaZomer/SoundWaveDistortionViaFPGA

Implementation on FPGA of a distortion effect in sound waves called "Overdrive" or "Clipping" as a final project of the couse Management and Analysis of Physics Dataset (mod.A).

Language: SystemVerilog - Size: 30.5 MB - Last synced at: 11 months ago - Pushed at: about 3 years ago - Stars: 4 - Forks: 1

lucarinelli/computer_architecture_project

Our project material for the Computer Architecture course for Computer Engineering students at Politecnico di Torino (Polytechnic University of Turin)

Language: VHDL - Size: 97.1 MB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 4 - Forks: 0

vinayak1998/Reflex-Tester

This project aims to test how fast you can respond after seeing a visual stimulus or rather hand-eye coordination.

Language: VHDL - Size: 1.02 MB - Last synced at: over 1 year ago - Pushed at: over 7 years ago - Stars: 4 - Forks: 0

Gabriele-bot/ALVEO-PYNQ_ML

Neural network inferences on Alveo cards with hls4ml framework

Language: Ada - Size: 786 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 1

DiegoRosales/Zybo_Sampler

Audio Sampler for Zybo

Language: C - Size: 43.1 MB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 1

shinesunnysom/Biofeedback-Game-System

CECS 490A/490B Course; Senior Project Design

Language: Verilog - Size: 742 KB - Last synced at: 23 days ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 0

MaharshSuryawala/Microprocessor-Without-Interlocked-Pipeline-Stages-MIPS

RISC based 8-bits five stage pipelined processor, operating at 585 MHz clock frequency with 19 I/O pins and 28 instructions having 5 Addressing formats. Tested on Xilinx Artix-7 FPGA.

Language: Verilog - Size: 5.53 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 1

0xastro/RTL_QAM

The project is designed using VHDL to realise the M-QAM modulation.

Language: VHDL - Size: 13.6 MB - Last synced at: about 1 year ago - Pushed at: about 5 years ago - Stars: 3 - Forks: 1

ctsiaousis/mipsMultiCycleProcessor 📦

A VHDL implementation of a MIPS processor with multicycle instruction fetching

Language: C - Size: 1.36 MB - Last synced at: over 1 year ago - Pushed at: about 5 years ago - Stars: 3 - Forks: 0

MossbauerLab/MessbauerTestEnvironment

FPGA Messbauer hardware (generator, emulation of signal from gamma-source registered and amplified

Language: Verilog - Size: 2.84 MB - Last synced at: about 1 year ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 1

ngiambla/qvmi

Quick Verilog Module Isolator - Isolates a design for testing.

Language: Verilog - Size: 233 KB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 3 - Forks: 0

trungnob/MicroBlaze

Language: LabVIEW - Size: 30.9 MB - Last synced at: over 1 year ago - Pushed at: about 7 years ago - Stars: 3 - Forks: 0

PZHengwf/post_iap_fpga

基于Xilinx Virtex-5在线更新FPGA外部FLASH，修改FPGA配置文件，完成IAP在线更新；

Size: 857 KB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 3 - Forks: 1

Jpfonseca/Reconfigurable_Computing 📦

Reconfigurable_Computing course

Language: VHDL - Size: 141 MB - Last synced at: about 2 years ago - Pushed at: almost 8 years ago - Stars: 3 - Forks: 0

SeungjaeLim/Efficient-Road-Repairs-System

[KAIST CS632] Road damage detection using YOLOv8 on Xilinx FPGA, repair estimation with vLLM-Serve Phi-3.5 FAISS RAG, and data management via GS1 EPCISv2 and React dashboard

Language: Python - Size: 86.4 MB - Last synced at: 17 days ago - Pushed at: 4 months ago - Stars: 2 - Forks: 0

Prithvish04/reconfigurable_project

Canny edge detection in HLS

Language: Jupyter Notebook - Size: 10.1 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 2 - Forks: 0

mabowers/xc2064-clock

Desk clock based on the Xilinx XC2064 FPGA

Language: OCaml - Size: 116 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 2 - Forks: 0

viktor-nikolov/ILI9488-Xilinx

ILI9488 TFT SPI display library for Xilinx SoC and FPGA

Language: C - Size: 51.7 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 2 - Forks: 1

Slatyo/SonarTracking

Small project to track things with a waterproof sonar sensor

Language: C++ - Size: 2.22 MB - Last synced at: 16 days ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

onegentig/VUT-FIT-INC2022-projekt 📦

Projekt (UART přijímací část) z předmětu Návrh číslicových systémů (INC), druhý semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2021/2022

Language: VHDL - Size: 255 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

Bassam-Kobasy/Vitis-IDE

This repo explain how to setup and install Vitis IDE for acceleration projects

Size: 32.2 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 1

aryan-programmer/axi_gen_and_sum_primes_fpga

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Language: TeX - Size: 191 KB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

Ryuzaki101/Programmable-logic-components

Xilinix VHDL Projects

Language: C - Size: 3.49 MB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 0

solomspd/RISC-V-CPU

RISC-V 5-stage pipeline RV32I implementation with forwarding in verilog with drivers to work on xilinx nexus a7 FPGA boards

Language: Verilog - Size: 1.15 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

majorlin/xloader

Xilinx FPGA loader

Language: Verilog - Size: 330 KB - Last synced at: over 1 year ago - Pushed at: about 5 years ago - Stars: 2 - Forks: 1

markus-k/rv32-soc

A simple RISC-V SoC based on picorv32

Language: VHDL - Size: 26.4 KB - Last synced at: 4 days ago - Pushed at: about 5 years ago - Stars: 2 - Forks: 0

erihsu/TinySoC

Arm cortex-m3 based SoC implementation used for simple car plane recognization

Language: V - Size: 38.5 MB - Last synced at: 12 months ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 1

andrsmllr/spartan3e_starter_devbrd

Play and learn with the Digilent Spartan3E-Starter board featuring a Xilinx Spartan-3E XC3S500E FPGA and various peripherals.

Size: 2.93 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 1

Elon-Wang/Breakout

Using the FPGA board Nexys Artix-7 to design a breakout game with vhdl language.

Language: VHDL - Size: 29.7 MB - Last synced at: 12 months ago - Pushed at: almost 6 years ago - Stars: 2 - Forks: 0

mcagriaksoy/DegreeAdjustableRadar

Zynq ZedBoard SoC Lecture Final Project, degree adjustable ultrasonic sensor application

Language: VHDL - Size: 219 KB - Last synced at: about 2 years ago - Pushed at: almost 6 years ago - Stars: 2 - Forks: 0

Sumegh-git/Xilinx-Innovation-Challenge

Team reverse_biased

Language: Python - Size: 15.1 MB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 1

sahilmgandhi/m152b-fall2018

CS M152B Codebase Fall 2018

Language: HTML - Size: 43.5 MB - Last synced at: 8 days ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 1

JoseCVieira/JacobiMethod-HwSw-Architecture

Implementation of Jacobi method in a co-processing architecture Hw/Sw using FPGA (Field Programmable Gate Array) ZYBO Zynq-7000 Development Board for Co-Project Hw/Sw course.

Language: VHDL - Size: 196 MB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 2 - Forks: 1