zedboard | Topic | Ecosyste.ms: Repos

Topic: "zedboard"

bperez77/xilinx_axidma

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.

Language: C - Size: 271 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 395 - Forks: 206

eliaskousk/parallella-riscv

RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards

Language: SystemVerilog - Size: 3.98 MB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 84 - Forks: 29

WangXuan95/Zynq-Tutorial

使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例

Language: C - Size: 49.4 MB - Last synced at: 11 months ago - Pushed at: over 1 year ago - Stars: 80 - Forks: 14

MeowLucian/SDR_FM_Radio

:radio: Using Software Designed Radio to transmit & receive FM signal

Language: Matlab - Size: 16.8 MB - Last synced at: about 2 months ago - Pushed at: about 7 years ago - Stars: 44 - Forks: 21

DLX4/zed_face

zedboard上基于FPGA+ARM的人脸识别智能监控系统。关键词：linux，zedboard，arm，fpga，人脸检测，人脸识别。

Language: C - Size: 17.7 MB - Last synced at: about 2 years ago - Pushed at: almost 9 years ago - Stars: 41 - Forks: 21

jiafulow/zedboard-guide

Size: 7.78 MB - Last synced at: almost 2 years ago - Pushed at: over 9 years ago - Stars: 32 - Forks: 14

FloyedShen/mnist_hls

Lenet for MNIST handwritten digit recognition using Vivado hls tool

Language: Objective-C - Size: 2.5 MB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 31 - Forks: 10

delhatch/Zynq_UDP

Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.

Language: C - Size: 146 KB - Last synced at: 27 days ago - Pushed at: about 4 years ago - Stars: 25 - Forks: 15

Goshik92/SHA256Hasher

SHA-256 IP core for ZedBoard (Zynq SoC)

Language: Verilog - Size: 15.5 MB - Last synced at: over 2 years ago - Pushed at: almost 7 years ago - Stars: 25 - Forks: 13

lvgl/lv_port_xilinx_zedboard_vitis

This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals

Language: C - Size: 82 MB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 22 - Forks: 5

sarthak268/Embedded_Logic_and_Design

This repository contains all labs done as a part of the Embedded Logic and Design course.

Size: 14.7 MB - Last synced at: about 1 year ago - Pushed at: almost 7 years ago - Stars: 21 - Forks: 2

splAcharya/DigitalOscilloscope_Zynq7000Soc

A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.

Size: 71.2 MB - Last synced at: 7 months ago - Pushed at: almost 5 years ago - Stars: 18 - Forks: 4

mmattioli/ZedBoard-OLED

Driving the OLED display on the ZedBoard

Language: VHDL - Size: 34.2 KB - Last synced at: almost 2 years ago - Pushed at: over 5 years ago - Stars: 17 - Forks: 12

delhatch/VGA_mem_mapped

Memory-mapped VGA display for Xilinx/Zynq/Zedboard, with demo code for using it.

Language: VHDL - Size: 32.2 MB - Last synced at: 3 months ago - Pushed at: over 7 years ago - Stars: 15 - Forks: 2

ugoleone/zedboard_image_processing_pipeline

FPGA based image processing pipeline using zedboard, able to accelerate openCV functions

Language: VHDL - Size: 152 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 8 - Forks: 1

delhatch/Zedboard_Mandel

Mandelbrot generator on the Zedboard. The image is output on the VGA port. Pure Verilog RTL, no ARM core.

Language: VHDL - Size: 24 MB - Last synced at: 3 months ago - Pushed at: over 7 years ago - Stars: 8 - Forks: 3

HYSUM-TOBBETU/AES-Encryption-Verilog-Pipelined-Implementation-128bit

Device: Zedboard xc7z020clg484-1, Clock Rate: 319 MHz, Tool: Vivado 2018.3, Language: Verilog

Language: Verilog - Size: 66.1 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 7 - Forks: 0

twosixlabs/ultrazed_dev

UltraZed Development

Language: C - Size: 93.3 MB - Last synced at: about 1 month ago - Pushed at: about 7 years ago - Stars: 7 - Forks: 4

eliaskousk/parallella-riscv-images

Parallella RISC-V Prebuilt Images

Size: 34.9 MB - Last synced at: almost 2 years ago - Pushed at: almost 9 years ago - Stars: 7 - Forks: 1

Inception-framework/debugger

A low-latency USB3-based JTAG debugger.

Language: VHDL - Size: 99.8 MB - Last synced at: 2 months ago - Pushed at: about 5 years ago - Stars: 6 - Forks: 1

Injabie3/dj-board

SFU - ENSC 452 (Advanced Digital System Design) Term Project: The Ultimate DJ Board using a Zedboard. Also mirrored on SFU CSIL's GitLab.

Language: VHDL - Size: 24.1 MB - Last synced at: 3 days ago - Pushed at: over 6 years ago - Stars: 6 - Forks: 1

delhatch/IIR_EQ

IIR audio filter in Verilog, running on Zedboard. Fractional integer coefficients.

Language: VHDL - Size: 45.1 MB - Last synced at: 3 months ago - Pushed at: over 7 years ago - Stars: 6 - Forks: 5

neeraj1397/Fast-Fourier-Transform-in-C

This repository contains the C code for ARM Implementation of FFT on Zynq-7000 APSoC from Xilinx.

Language: C - Size: 2.15 MB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 5 - Forks: 2

zslwyuan/Zedboard_Intergrating_HLS_IP_AND_DDR

This is a project integrating HLS IP and CortexA9 on Zynq. This project implements DDR3 random access with HLS. The Cortex A9 will print the result via UART.

Language: VHDL - Size: 54.2 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 5 - Forks: 4

Goshik92/fsearch

FastSearch is a project intended to increase the speed of string searching by using the FPGA technology

Language: Verilog - Size: 28 MB - Last synced at: over 2 years ago - Pushed at: almost 7 years ago - Stars: 5 - Forks: 3

dougbrion/fpga-image-processing

Low latency FPGA based image processing (Zedboard)

Language: VHDL - Size: 4.51 MB - Last synced at: 6 months ago - Pushed at: over 8 years ago - Stars: 5 - Forks: 1

arokasprz100/HDL-Safe 📦

Simple safe lock mechanism written in SystemVerilog.

Language: SystemVerilog - Size: 60.4 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 4 - Forks: 0

michaelkimmer/zedboard_adrv9002_project

Implementation of an IEEE 802.11p PHY realitime receiver in VHDL on ZedBoard and ADRV9002. Master's thesis at CTU in Prague FEE.

Language: VHDL - Size: 3.57 GB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 3 - Forks: 3

ilaydayaman/Bachelor_Thesis

Implementation of Nist Tests on a Chaotic Random Number Generator Inside a System on Chip (Zynq®-7000 All Programmable SoC)

Size: 3.31 MB - Last synced at: almost 2 years ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 0

cgruda/repo

ZedBoard FPGA based Convolutional Neural Network (CNN) accelerator

Language: C++ - Size: 657 MB - Last synced at: 4 months ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 2

zslwyuan/Zedboard-xfOpenCV-Optical-Flow

xfOpenCV Optical Flow implemented on Zedboard with built aarch32 OpenCV libraries

Language: C++ - Size: 502 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 0

sagniknitr/Reconfigurable-Lab-Project

8 bit MCU design in Zedboard

Language: VHDL - Size: 975 KB - Last synced at: about 2 years ago - Pushed at: about 8 years ago - Stars: 3 - Forks: 0

dwij2812/UART-Spectrum-Analyzer-for-Serial-Devices

The following Script can be used to generate certain mathematical functions on a micro controller or FPGA Device connected in serial based on the configuration selected by the the user and collect realtime data of the signal as generated by the device for spectrum analysis.

Language: VHDL - Size: 15 MB - Last synced at: 24 days ago - Pushed at: 24 days ago - Stars: 2 - Forks: 1

r0tary/FPGA-Audio-Visualizer

An audio visualizer implemented on a Zedboard FPGA, that takes in audio and outputs it on a VGA supported monitor

Language: VHDL - Size: 306 MB - Last synced at: 4 months ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 0

Fivefold/SRCNN

Super Resolution Convolutional Neural Network (SRCNN) for Python/Torch, Numpy and Avnet's ZedBoard

Language: VHDL - Size: 12.1 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0

amamory/hermes-noc-tester-vivado-ip

Vivado test IP for Hermes NoC Router

Language: VHDL - Size: 40 KB - Last synced at: 3 months ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 0

mcagriaksoy/DegreeAdjustableRadar

Zynq ZedBoard SoC Lecture Final Project, degree adjustable ultrasonic sensor application

Language: VHDL - Size: 219 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 2 - Forks: 0

delhatch/Multi_IIR

Multi-band IIR filter in Verilog. Uses time-domain multiplexing of a single, fixed-point, IIR filter to create a 27-band filter.

Language: VHDL - Size: 63.1 MB - Last synced at: 3 months ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 1

mmattioli/ZedBoard-LED-Button

Illuminate LEDs on the ZedBoard using push buttons

Language: Tcl - Size: 10.7 KB - Last synced at: almost 2 years ago - Pushed at: about 8 years ago - Stars: 2 - Forks: 1

tsotnep/ETSE_GDSP Fork of ovieOsimiry/ETSE_GDSP

Repository for DSP matrix multiplier IP core and other related side projects

Language: VHDL - Size: 319 MB - Last synced at: over 2 years ago - Pushed at: about 8 years ago - Stars: 2 - Forks: 0