Topic: "fpga-soc"
lnis-uofu/OpenFPGA
An Open-source FPGA IP Generator
Language: Verilog - Size: 90 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 1,011 - Forks: 179
trivialmips/nontrivial-mips
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
Language: SystemVerilog - Size: 20.4 MB - Last synced at: 7 days ago - Pushed at: over 5 years ago - Stars: 601 - Forks: 102
JunningWu/Learning-NVDLA-Notes
NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:junning.wu@ia.ac.cn
Size: 4 MB - Last synced at: 5 months ago - Pushed at: almost 7 years ago - Stars: 226 - Forks: 66
dpretet/axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
Language: SystemVerilog - Size: 459 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 169 - Forks: 30
timvideos/HDMI2USB-litex-firmware
A version of the HDMI2USB firmware based around LiteX tools produced by @Enjoy-Digital (based on misoc+migen created by @M-Labs)
Language: Python - Size: 8.23 MB - Last synced at: over 1 year ago - Pushed at: almost 6 years ago - Stars: 139 - Forks: 74
ultraembedded/riscv_soc
Basic RISC-V Test SoC
Language: Verilog - Size: 6.1 MB - Last synced at: 3 months ago - Pushed at: over 6 years ago - Stars: 138 - Forks: 30
ZipCPU/openarty
An Open Source configuration of the Arty platform
Language: Verilog - Size: 14.2 MB - Last synced at: 3 months ago - Pushed at: almost 2 years ago - Stars: 130 - Forks: 24
azonenberg/antikernel
The Antikernel operating system project
Language: Verilog - Size: 8.67 MB - Last synced at: about 23 hours ago - Pushed at: over 5 years ago - Stars: 119 - Forks: 10
esa-tu-darmstadt/tapasco
The Task Parallel System Composer (TaPaSCo)
Language: Verilog - Size: 107 MB - Last synced at: 6 months ago - Pushed at: 10 months ago - Stars: 108 - Forks: 26
strath-sdr/rfsoc_qpsk
PYNQ example of using the RFSoC as a QPSK transceiver.
Language: VHDL - Size: 65 MB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 108 - Forks: 47
trivialmips/TrivialMIPS
MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
Language: SystemVerilog - Size: 84.3 MB - Last synced at: 7 days ago - Pushed at: over 6 years ago - Stars: 108 - Forks: 35
michaelehab/AES-Verilog
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
Language: Verilog - Size: 8.73 MB - Last synced at: 3 months ago - Pushed at: over 3 years ago - Stars: 105 - Forks: 26
tommythorn/yarvi
Yet Another RISC-V Implementation
Language: Roff - Size: 2.82 MB - Last synced at: 22 days ago - Pushed at: about 1 year ago - Stars: 97 - Forks: 24
strath-sdr/rfsoc_sam
RFSoC Spectrum Analyser Module on PYNQ.
Language: VHDL - Size: 133 MB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 86 - Forks: 24
Obijuan/Z80-FPGA
Z80 CPU for OpenFPGAs, with Icestudio
Language: Assembly - Size: 4.45 MB - Last synced at: 7 months ago - Pushed at: over 1 year ago - Stars: 77 - Forks: 18
jingpu/Halide-HLS
HLS branch of Halide
Language: C++ - Size: 239 MB - Last synced at: over 1 year ago - Pushed at: over 7 years ago - Stars: 74 - Forks: 21
ryuz/jelly
Original FPGA platform
Language: Verilog - Size: 30.7 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 70 - Forks: 17
tommythorn/fpgammix
Partial implementation of Knuth's MMIX processor (FPGA softcore)
Language: C - Size: 479 KB - Last synced at: 22 days ago - Pushed at: 6 months ago - Stars: 54 - Forks: 9
micro-FPGA/engine-V
SoftCPU/SoC engine-V
Language: Verilog - Size: 14.6 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 54 - Forks: 7
tommythorn/yari
YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.
Language: C - Size: 30.8 MB - Last synced at: 22 days ago - Pushed at: 11 months ago - Stars: 44 - Forks: 9
arm-university/Fundamentals-of-System-on-Chip-Design-on-Arm-Cortex-M-Microcontrollers
A textbook on understanding system on chip design
Size: 61.6 MB - Last synced at: 4 months ago - Pushed at: 5 months ago - Stars: 40 - Forks: 10
strath-sdr/rfsoc_radio
PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.
Language: VHDL - Size: 55.4 MB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 37 - Forks: 11
robseb/HPS2FPGAmapping
SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
Language: Verilog - Size: 11 MB - Last synced at: 7 months ago - Pushed at: over 4 years ago - Stars: 37 - Forks: 13
Domipheus/ArtyS7-RPU-SoC
Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.
Language: VHDL - Size: 18.8 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 33 - Forks: 6
ultraembedded/fpga_test_soc
A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
Language: C - Size: 1.11 MB - Last synced at: 4 months ago - Pushed at: over 5 years ago - Stars: 33 - Forks: 12
ZipCPU/s6soc
CMod-S6 SoC
Language: Verilog - Size: 2.8 MB - Last synced at: over 2 years ago - Pushed at: almost 8 years ago - Stars: 33 - Forks: 5
arm-university/Modern-System-on-Chip-Design-on-Arm
A textbook on system on chip design using Arm Cortex-A
Size: 15.9 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 32 - Forks: 8
dpretet/friscv
RISCV CPU implementation in SystemVerilog
Language: SystemVerilog - Size: 4.3 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 31 - Forks: 5
raetro/sdk-docker-fpga
Intel Quartus Prime Synthesis Engine for Docker
Language: Dockerfile - Size: 847 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 31 - Forks: 7
ustb-owl/TinyMIPS
The Project TinyMIPS is dedicated to enabling undergraduates to build a complete computer system from scratch.
Language: C++ - Size: 31.6 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 31 - Forks: 6
fpw/SoCDP8
A SoC implementation of a PDP-8/I for the PiDP-8/I console
Language: C - Size: 37.2 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 29 - Forks: 4
hipersys-team/lightning
[SIGCOMM 2023] Lightning: A Reconfigurable Photonic-Electronic SmartNIC for Fast and Energy-Efficient Inference
Language: Verilog - Size: 14 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 28 - Forks: 3
HRL-Laboratories/spinqick
An open-source control library for electrostatically confined spin-qubits developed by HRL Quantum and based on the Quantum Instrumentation Control Kit (QICK).
Language: Python - Size: 949 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 25 - Forks: 1
hex-five/multizone-fpga Fork of sifive/freedom
This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 SoC is Hex Five's official reference platform for its MultiZone Security Trusted Execution Environment and MultiZone Security Trusted Firmware. The X300 is an enhanced secure version of the - now archived - SiFive's Freedom E300 Platform built around the RISC-V Rocket chip originally developed at U.C. Berkeley.
Language: Scala - Size: 212 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 24 - Forks: 5
KastnerRG/infinitam_fpga
InfiniTAM on FPGA
Language: C++ - Size: 6.28 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 23 - Forks: 2
BLangOS/VexRiscV_with_HW-GDB_Server
VexRiscV system with GDB-Server in Hardware
Language: VHDL - Size: 346 KB - Last synced at: 4 months ago - Pushed at: over 2 years ago - Stars: 21 - Forks: 4
splinedrive/lets_build_a_compiler_for_riscv
A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw
Language: C - Size: 2.65 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 21 - Forks: 4
nhasbun/de10nano_fpga_linux_config
DE10-Nano FPGA Configuration from Linux. Software to configure the FPGA portion of the Cyclone V SoC.
Language: C - Size: 8.79 KB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 21 - Forks: 6
fmhess/fmh_gpib_core
GPIB IEEE 488.1 core
Language: VHDL - Size: 511 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 18 - Forks: 8
splAcharya/DigitalOscilloscope_Zynq7000Soc
A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.
Size: 71.2 MB - Last synced at: 12 months ago - Pushed at: over 5 years ago - Stars: 18 - Forks: 4
leastrobino/acoustic-levitation
Acoustic levitation on SoC FPGA (DE0-Nano-SoC). Notice: this repository has moved to GitLab. All issues and pull requests should be created there.
Language: VHDL - Size: 190 MB - Last synced at: almost 2 years ago - Pushed at: almost 7 years ago - Stars: 18 - Forks: 4
siorpaes/SimpleSoC
Very simple Cortex-M1 SoC design based on ARM DesignStart
Language: C - Size: 206 KB - Last synced at: about 1 month ago - Pushed at: almost 4 years ago - Stars: 17 - Forks: 3
ASP-SoC/ASP-SoC
Audio Signal Processing SoC
Language: VHDL - Size: 33.9 MB - Last synced at: about 1 year ago - Pushed at: over 7 years ago - Stars: 17 - Forks: 8
mcagriaksoy/VHDL-FPGA-LAB_PROJECTS
My Lab Assigments from Bachelor Degree, This repo includes the projects for digital systems II Lecture (EEM334)
Language: VHDL - Size: 575 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 14 - Forks: 2
mikeroyal/FPGA-Guide
FPGA Guide
Language: Verilog - Size: 25.4 KB - Last synced at: 7 months ago - Pushed at: almost 4 years ago - Stars: 12 - Forks: 2
dawsonjon/chips_v
RISC-V System on Chip Builder
Language: Verilog - Size: 1.07 MB - Last synced at: 3 months ago - Pushed at: about 5 years ago - Stars: 12 - Forks: 2
fast-codesign/FAST-OpenBox-S4
FAST implemented on Xilinx Zynq7000 SoC board
Language: Makefile - Size: 16.7 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 12 - Forks: 5
Choaib-ELMADI/fpga-programming-for-beginners
A collection of notes, summaries, and projects based on the book "FPGA Programming for Beginners" by Frank Bruno.
Language: Tcl - Size: 30.4 MB - Last synced at: 8 months ago - Pushed at: about 1 year ago - Stars: 11 - Forks: 1
Goshik92/multicore-nios
Matrix multiplication on multiple Nios II cores
Language: C - Size: 399 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 11 - Forks: 6
peacekeeper228/labHPS
working with HPS
Language: C - Size: 17.6 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 10 - Forks: 0
Stuart0l/BNN
HLS code for a BNN accelerator
Language: C++ - Size: 2.31 MB - Last synced at: over 2 years ago - Pushed at: about 7 years ago - Stars: 10 - Forks: 7
RISMicroDevices/RMM4NC30F2X 📦
Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022
Language: VHDL - Size: 31.3 MB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 9 - Forks: 1
daniel-santos-7/leaf
Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.
Language: VHDL - Size: 665 KB - Last synced at: about 3 hours ago - Pushed at: about 5 hours ago - Stars: 8 - Forks: 3
machdyne/zeitlos
Zeitlos SOC/OS
Language: Verilog - Size: 1.18 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 8 - Forks: 2
nobotro/fpga_riscv_cpu
fpga verilog risc-v rv32i cpu
Language: Verilog - Size: 97.3 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 8 - Forks: 2
ugoleone/zedboard_image_processing_pipeline
FPGA based image processing pipeline using zedboard, able to accelerate openCV functions
Language: VHDL - Size: 152 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 8 - Forks: 1
mcci-catena/catena-riscv32-fpga
RISC-V 32-bit core for MCCI Catena 4710
Language: Verilog - Size: 114 KB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 8 - Forks: 2
Choaib-ELMADI/getting-started-with-vhdl
Getting started with VHDL: Very High Speed Integrated Circuit Hardware Description Language.
Language: VHDL - Size: 38.5 MB - Last synced at: 28 days ago - Pushed at: 8 months ago - Stars: 7 - Forks: 0
peacekeeper228/multi-core-processor
Upgrade of SchoolMIPS single-core processor
Language: Verilog - Size: 3.91 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 7 - Forks: 0
NukaCola-Quantum/MBIST-verilog
A Flyweight MBIST Block - FPGA synthesizable, Multi-algorithm integrated
Language: Verilog - Size: 22.5 KB - Last synced at: over 2 years ago - Pushed at: almost 7 years ago - Stars: 7 - Forks: 2
EngineerMichael/-Robotic-Arm---Haddington-Dynamics-Robotics-Engineering-
⎔ Automation in 3D-Printed Robotics in C & JS (Revising Custom JavaScript Source Code Files)
Language: JavaScript - Size: 4 MB - Last synced at: about 2 months ago - Pushed at: 8 months ago - Stars: 6 - Forks: 0
khldunsaid/Designed-and-Implemented-a-multicore-processor-using-FPGA.
This project aims to learn how to perform hardware-software co-design of an FPGA-based multi-core processor system and parallelize applications to the multi-core processor and optimize the performance using various techniques.
Language: C - Size: 80.1 MB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 6 - Forks: 1
wubinary/two_stream_soc
SOC of two_stream action recognition on ZCU102
Language: Jupyter Notebook - Size: 35.7 MB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 6 - Forks: 1
ikwzm/FPGA-SoC-U-Boot-ZYBO-Z7
U-Boot image for ZYBO-Z7
Language: Shell - Size: 2.96 MB - Last synced at: 22 days ago - Pushed at: over 7 years ago - Stars: 6 - Forks: 2
ASP-SoC/ASP-SoC.github.io
Audio Signal Processing SoC Project Website
Language: HTML - Size: 3.96 MB - Last synced at: about 1 year ago - Pushed at: over 8 years ago - Stars: 6 - Forks: 1
Choaib-ELMADI/riscv-on-de2-soc-fpga
A simplified RISC-V processor implemented in Verilog and deployed on the DE-2 SoC FPGA board.
Language: Verilog - Size: 24.4 MB - Last synced at: 4 months ago - Pushed at: 5 months ago - Stars: 5 - Forks: 2
Choaib-ELMADI/working-with-fpga-and-mips
A collection of practical sessions exploring FPGA programming and MIPS-based systems using the ALTERA Cyclone V DE-1 SoC board.
Language: Verilog - Size: 11.2 MB - Last synced at: about 2 months ago - Pushed at: 7 months ago - Stars: 5 - Forks: 0
j-schacht/xilinx_zcu102_trustzone_demo
Tutorial and base project: TEE on AMD Zynq UltraScale+ using Arm TrustZone
Language: C - Size: 69 MB - Last synced at: 6 days ago - Pushed at: over 1 year ago - Stars: 5 - Forks: 2
somdipdey/MAT-CNN-SOPC
MAT-CNN-SOPC: Motionless Analysis of Traffic Using Convolutional Neural Networks on System-On-a-Programmable-Chip
Language: HTML - Size: 16.9 MB - Last synced at: 7 months ago - Pushed at: almost 7 years ago - Stars: 5 - Forks: 3
Goshik92/fsearch
FastSearch is a project intended to increase the speed of string searching by using the FPGA technology
Language: Verilog - Size: 28 MB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 5 - Forks: 3
ikwzm/FPGA-SoC-U-Boot-DE10-Nano
U-Boot image for DE10-Nano
Language: Shell - Size: 251 KB - Last synced at: 22 days ago - Pushed at: over 7 years ago - Stars: 5 - Forks: 2
Choaib-ELMADI/working-with-fpga-and-vhdl
A collection of practical FPGA and VHDL projects using the ALTERA Cyclone V DE-1 SoC board.
Language: VHDL - Size: 12.4 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 4 - Forks: 0
QuorumComp/hc800
HC800 Home Computer core
Language: Verilog - Size: 1.37 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 4 - Forks: 0
Nathen-Smith/FPGA-super-mario-bros
FPGA SOC Mario NES in SystemVerilog. Built on a DE-10 Lite FPGA, synthesized in Quartus Prime 18.1
Language: Verilog - Size: 1.02 MB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 4 - Forks: 2
icebreaker-fpga/icetwang
An iCEBreaker-Bitsy based 1D game system, using intelligent LED strings and springs as controllers.
Language: Rust - Size: 3.7 MB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 4 - Forks: 1
ikwzm/FPGA-SoC-U-Boot-PYNQ-Z1
U-Boot image for PYNQ-Z1
Language: Shell - Size: 1.34 MB - Last synced at: 22 days ago - Pushed at: over 7 years ago - Stars: 4 - Forks: 1
10x-Engineers/Infinite-ISP_LinuxCameraStack
Extending Linux support to enable Infinite-ISP on FPGA for the development of a libcamera-based camera application stack.
Language: C++ - Size: 41.1 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 3 - Forks: 4
dohuyminhdung/PQC_Dilithium
Language: SystemVerilog - Size: 98.6 KB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 3 - Forks: 0
aiegoo/documentation
my project documentattion
Language: Jupyter Notebook - Size: 4.65 GB - Last synced at: 16 days ago - Pushed at: 17 days ago - Stars: 3 - Forks: 0
jiadong5/ECE385_SP23_ZJUI
Final Project third-perspective-shooting video game PokeHead and some other lab codes and design of ECE385 Digital Systems Laboratory
Language: C - Size: 68.7 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0
Divyathali/FPGA-Routing-placement---Best-way
The published IEEE paper tells about the basic details of this project
Language: C - Size: 102 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0
DiegoRosales/Zybo_Sampler
Audio Sampler for Zybo
Language: C - Size: 43.1 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 1
pedrovt/cr-labs
Labs of the Reconfigurable Computing course, University of Aveiro
Language: VHDL - Size: 108 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 1
cajt/cmod-a7-35t_leon3
GRLIB GPL support for Digilent CMOD A7 35T board
Language: VHDL - Size: 2.2 MB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 3 - Forks: 1
topologicalhurt/Thesis
Fpga thesis project. An intelligent hardware scheduling algorithm focused on common signal chains.
Language: Python - Size: 136 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 2 - Forks: 1
Insper/Embarcados-Avancados
SoC and Embedded Linux
Language: JavaScript - Size: 81 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 2 - Forks: 11
RickBarretto/sobel
Sobel is a border recognizer CLI application that applies multiples filter algorithms and uses the Laplace MPU for convolution. This project was made for the 3rd PBL of TEC499 - Digital Systems.
Language: Verilog - Size: 9.63 MB - Last synced at: 29 days ago - Pushed at: 5 months ago - Stars: 2 - Forks: 1
mnemocron/my-discrete-fpga
My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.
Language: VHDL - Size: 9.57 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0
open-photonics/lightning
[SIGCOMM 2023] Lightning: A Reconfigurable Photonic-Electronic SmartNIC for Fast and Energy-Efficient Inference
Language: Verilog - Size: 14 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0
Koyama-Tsubasa/VLSI_System_Design
Coursework of NTHU CS512000 VLSI System Design
Language: C - Size: 20.2 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0
aidanrhind/License_Plate_Detection_yolov4_KV260
Custom YoloV4 Darknet/Tensorflow model for license plate detection on the AMD-Xilinx Kria KV260 Vision-AI starter Kit. Utilize transfer learning to create your own custom object detecion model on a custom dataset, quantize and compile in Vitis-AI for easy deployment and evaluation on FPGA.
Language: Shell - Size: 7.81 KB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0
sdonchez/petalinux-zedboard-test
A simple proof of concept project demonstrating the use of PetaLinux in conjunction with Vivado to deploy a Linux environment alongside programable logic on a heterogeneous System on a Chip (SoC).
Language: HTML - Size: 664 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0
mukullokhande99/fifo_hardware_fpga
FIFO implemented on FPGA Spartan 6
Language: Rich Text Format - Size: 21.4 MB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 1
raetro/raetro_system_kernel
Rætro Linux Kernel Source
Language: C - Size: 218 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0
cyber-murmel/nmigen-wishbone-examples
A collection of nMigen examples based on the OpenCores WISHBONE Tutorial https://cdn.opencores.org/downloads/wbspec_b4.pdf#page=91
Language: Python - Size: 298 KB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 0
htanwar922/VHDL-Numerical-Overcurrent-Relay
Fixed and float packages. Overcurrent relay.
Language: VHDL - Size: 80.1 KB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 2 - Forks: 0
timvideos/qemu-litex Fork of mithro/qemu-litex
Language: C - Size: 119 MB - Last synced at: over 1 year ago - Pushed at: about 7 years ago - Stars: 2 - Forks: 2
gergo-papp/SystemOnChip-ImageProcessing-myRIO
Image Processing Algorithms on System-on-Chip FPGA Devices using a myRIO as hardware and LabVIEW as software
Language: LabVIEW - Size: 6.27 MB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 3
ikwzm/FPGA-SoC-U-Boot-DE0-Nano-SoC
U-Boot image for DE0-Nano-SoC
Language: Shell - Size: 329 KB - Last synced at: 22 days ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 1
nhasbun/uart_16550_core_lib
Altera wrappers for C applications using Altera's 16550 UART Core through Avalon Bus on Cyclone V.
Language: C - Size: 7.81 KB - Last synced at: over 2 years ago - Pushed at: almost 8 years ago - Stars: 2 - Forks: 2