openhwgroup/cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Language: Assembly - Size: 139 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 2,525 - Forks: 792

VUnit/vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

Language: VHDL - Size: 14 MB - Last synced at: 29 days ago - Pushed at: about 2 months ago - Stars: 775 - Forks: 276

SystemRDL/PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Language: Python - Size: 918 KB - Last synced at: 26 days ago - Pushed at: 26 days ago - Stars: 66 - Forks: 47

nelsoncsc/ISP_UVM

A Framework for Design and Verification of Image Processing Applications using UVM

Language: SystemVerilog - Size: 499 KB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 64 - Forks: 27

pulp-platform/morty

A SystemVerilog source file pickler.

Language: Rust - Size: 916 KB - Last synced at: 6 days ago - Pushed at: 9 months ago - Stars: 57 - Forks: 6

nelsoncsc/easyUVM

A simple UVM example with DPI

Language: SystemVerilog - Size: 7.81 KB - Last synced at: over 2 years ago - Pushed at: almost 8 years ago - Stars: 28 - Forks: 12

pulp-platform/uvm-components

Contains commonly used UVM components (agents, environments and tests).

Language: SystemVerilog - Size: 452 KB - Last synced at: over 2 years ago - Pushed at: almost 7 years ago - Stars: 21 - Forks: 13

pulp-platform/axi_mem_if

Simple single-port AXI memory interface

Language: SystemVerilog - Size: 62.5 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 19 - Forks: 19

NikhilMukraj/spiking-neural-networks-hardware

An FPGA design for simulating biological neurons

Language: SystemVerilog - Size: 437 KB - Last synced at: 21 days ago - Pushed at: 12 months ago - Stars: 14 - Forks: 0

icglue/icglue

A Tcl-Library for scripted HDL generation

Language: Tcl - Size: 1.6 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 12 - Forks: 2

vinodsake/Last-Level-Cache-Simulator

Language: SystemVerilog - Size: 736 KB - Last synced at: over 1 year ago - Pushed at: over 8 years ago - Stars: 9 - Forks: 4

stineje/ecen4243S25

Spring 2025 ecen4243 Computer Architecture Lab Material

Language: HTML - Size: 101 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 8 - Forks: 23

BertVerrycken/BERT

Bit-Efficient Replicator Tech for X, Y, Z axis motor control (3D printers)

Language: VHDL - Size: 52.7 KB - Last synced at: 7 months ago - Pushed at: almost 5 years ago - Stars: 8 - Forks: 1

snbk001/100DaysofRTL

100DaysofRTL: basic logic gates, mux, half and full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector with Moore, Edge Detector with Mealy

Language: SystemVerilog - Size: 120 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 7 - Forks: 2

SalomeDevkule7/Neural-Network-Layer-Generator

Application Specific Integrated Circuit(ASIC)

Language: SystemVerilog - Size: 127 KB - Last synced at: 7 months ago - Pushed at: about 7 years ago - Stars: 7 - Forks: 3

nelsoncsc/basic_uvmc_oct

A simple UVM testbench using UVM Connect and Octave

Language: SystemVerilog - Size: 7.81 KB - Last synced at: over 2 years ago - Pushed at: almost 8 years ago - Stars: 7 - Forks: 0

ghosh17/DualCoreProcessor

ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor

Language: SystemVerilog - Size: 298 KB - Last synced at: over 2 years ago - Pushed at: almost 8 years ago - Stars: 6 - Forks: 2

ssayin/riscv32-cosim-model

RISC-V processor co-simulation using SystemVerilog HDL and UVM.

Language: SystemVerilog - Size: 4.37 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 5 - Forks: 0

mateuspinto/simplified-mips-pipeline

A synthesizable simplified MIPS written in System Verilog

Language: SystemVerilog - Size: 22.5 KB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 4 - Forks: 0

vinodsake/8-Bit-5-Stage-Microprocessor-Design

Language: SystemVerilog - Size: 1.87 MB - Last synced at: over 1 year ago - Pushed at: over 7 years ago - Stars: 4 - Forks: 0

yuri-panchul/tt08-adder-with-flow-control Fork of TinyTapeout/tt08-verilog-template

Submission for Tiny Tapeout 8 - Verilog HDL Projects. An adder with a separate flow control for each argument and the result.

Language: SystemVerilog - Size: 43.9 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 3 - Forks: 1

stineje/dldfall2023

This repository contains information about Digital Logic Design (ecen 3233) laboratory elements for Fall 2023.

Language: TeX - Size: 62.1 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 3 - Forks: 3

pulp-platform/axi2per

AXI to Peripheral Interconnect

Language: SystemVerilog - Size: 36.1 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 1

jiadong5/ECE385_SP23_ZJUI

Final Project third-perspective-shooting video game PokeHead and some other lab codes and design of ECE385 Digital Systems Laboratory

Language: C - Size: 68.7 MB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 0

CaglayanDokme/SystemVerilogExercises

This is a repo where I share the System Verilog exercises that I worked on. Contributions and suggestions are welcome

Language: SystemVerilog - Size: 222 KB - Last synced at: 11 days ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 1

hcyang99/rv32-core

Arbitary superscalar out-of-order RV32I core, with instruction prefetching and write-back no-write-allocate DCache.

Language: SystemVerilog - Size: 74.3 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 2

SvrAdityaReddy/Inter_Device_Communication_Protocols

Verilog Codes of various Inter Device Communication Protocols

Language: SystemVerilog - Size: 377 KB - Last synced at: almost 2 years ago - Pushed at: about 7 years ago - Stars: 3 - Forks: 1

arhamhashmi01/rv32i-sv

This repository contain the implementation of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on System Verilog

Language: SystemVerilog - Size: 38.1 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 2

DuinOS/AprendaFPGA

Algumas anotações de quem está aprendendo a sintetizar seu próprio microcontrolador em FPGA.

Size: 23.4 KB - Last synced at: 6 days ago - Pushed at: about 4 years ago - Stars: 2 - Forks: 0

alanmimms/kl10

KL10PV (also called "model B") CPU implemented in SystemVerilog for Xilinx FPGA from MP00301_KL10PV_Jun80 PDFs trying to remain faithful to the original while I learn Verilog

Language: SystemVerilog - Size: 223 MB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 2 - Forks: 0

0xD503/SystemVerilog-Modules

Common SystemVerilog/Verilog modules

Language: SystemVerilog - Size: 46.9 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 2 - Forks: 0

himingway/Parallel_Multiplier

A Parallel Multiplier Using SystemVerilog HDL

Language: SystemVerilog - Size: 324 KB - Last synced at: over 2 years ago - Pushed at: about 7 years ago - Stars: 2 - Forks: 0

nelsoncsc/basic_uvmc

A simple testbench with two refmods using UVM Connect

Language: SystemVerilog - Size: 9.77 KB - Last synced at: over 2 years ago - Pushed at: almost 8 years ago - Stars: 2 - Forks: 2

Maharishi1313/little_proc

RISC-V RV32IM Core

Language: C++ - Size: 7.57 MB - Last synced at: 30 days ago - Pushed at: 30 days ago - Stars: 1 - Forks: 0

pulp-platform/apb_fll_if

Control interface for FLL

Language: SystemVerilog - Size: 33.2 KB - Last synced at: 30 days ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 11

eshansurendra/UART-FPGA

This repository documents a project undertaken as part of the EN2111 Electronic Circuit Design module at the University of Moratuwa, focusing on the implementation of a UART communication link between two FPGA boards.

Language: SystemVerilog - Size: 3.5 MB - Last synced at: 4 months ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

Dipto9999/Scrolling_Display_DE1-SoC

Scrolling Display Implemented With Digital Design Concepts on De1-SoC

Language: SystemVerilog - Size: 3.09 MB - Last synced at: about 1 month ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

snyderth/SCARA_robot

A SCARA topoology robotic arm

Language: Python - Size: 390 MB - Last synced at: almost 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

mateuspinto/FPGA_SystemVerilog_MIPS_Pipeline-TP1-OC2-UFV

A complete hardware description of a pipeline MIPS processor in SystemVerilog that can execute integer assembly code implemented on the Altera DE2-115 FPGA. It also has the ALMa Mips Mounter built-in.

Language: SystemVerilog - Size: 2.78 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

NishadSaraf/Fibonacci-Sequence-Generator

Synthesizable hardware block that generates Fibonacci sequence based on the start value and order

Language: SystemVerilog - Size: 218 KB - Last synced at: over 2 years ago - Pushed at: almost 8 years ago - Stars: 1 - Forks: 0

nelsoncsc/basicSV

Very basic SystemVerilog examples

Language: SystemVerilog - Size: 1.29 MB - Last synced at: over 2 years ago - Pushed at: over 8 years ago - Stars: 1 - Forks: 0

SemenovMD/eth-sv

Ethernet SystemVerilog UDP/IP ARP ICMP AXI Stream

Language: SystemVerilog - Size: 1.02 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 0 - Forks: 0

VLSIJEXA/System-Verilog

learning system verilog

Language: SystemVerilog - Size: 17.6 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

ubyhzargam/System-Verilog

This repository contains System Verilog codes. These codes were written while learning system verilog. Will be updated almost daily as I learn more and more

Language: SystemVerilog - Size: 85 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

TahirZia-1/Digital-Clock-Verilog

This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.

Language: Tcl - Size: 166 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

Kevin-Caldwell/SimpleProcessor

Simple Single Bus RISCV Processor

Language: SystemVerilog - Size: 604 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

xver/icecream_sv

IceCream for SystemVerilog: Never use $display and `uvm_info to debug SystemVerilog again.

Language: SystemVerilog - Size: 216 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

aakash-n-gupta/ASICBlocks

System Level Simulation and ASIC hardening flow for various designs using Systemverilog, Verilator and OpenROAD

Language: Verilog - Size: 38.1 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

damian95a/Analog-signal-generator

FPGA based analog signal generator with DAC

Language: Verilog - Size: 461 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

z4chh/FPGA_Slot_Machine

A slot machine created in System Verilog. It was built, simulated, synthesized, and implemented in Vivado, for use on the Xilinx Basys 3 board.

Language: SystemVerilog - Size: 12.7 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

jaycordaro/half-band-filter

An implementation of an FIR half-band filter, from MATLAB floating point to SystemVerilog fixed point

Language: SystemVerilog - Size: 648 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

fightforit/SystemVerilog-Design-Blocks-Common-Use-Cases-and-Examples

Language: SystemVerilog - Size: 20.5 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

prithvi-narayan-bhat/Custom_RISC_Implementation

An attempt at making a customised RISC processor with five pipelined stages and supporting all RISC-V instruction set

Language: SystemVerilog - Size: 72.7 MB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

achakraborty2591/Learn-SystemVerilog

This repository contains the source files for the SystemVerilog Documentation Website

Language: JavaScript - Size: 357 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

mm-mehran79/networkPacket_stuffOrData

the module is also known as sigma delta

Language: SystemVerilog - Size: 3.04 MB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

abdullahqutb/cs223Project

Bilkent University CS223 Lab Project

Language: HTML - Size: 3.01 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0

0xD503/ARM-Multy-Cycle_Processor

ARM Multi Cycle Processor Core HDL Description

Language: SystemVerilog - Size: 37.1 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0

0xD503/Digital-music-project

Laboratory work project

Language: SystemVerilog - Size: 196 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0