verilator | Topic | Ecosyste.ms: Repos

Topic: "verilator"

verilator/verilator

Verilator open-source SystemVerilog simulator and lint system

Language: C++ - Size: 61 MB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 2,822 - Forks: 649

ultraembedded/riscv

RISC-V CPU Core (RV32IM)

Language: Verilog - Size: 5.27 MB - Last synced at: about 1 month ago - Pushed at: over 3 years ago - Stars: 1,398 - Forks: 251

ZipCPU/zipcpu

A small, light weight, RISC CPU soft core

Language: Verilog - Size: 256 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1,289 - Forks: 154

ultraembedded/biriscv

32-bit Superscalar RISC-V CPU

Language: Verilog - Size: 2.98 MB - Last synced at: 19 days ago - Pushed at: over 3 years ago - Stars: 980 - Forks: 164

chipsalliance/Cores-VeeR-EH1

VeeR EH1 core

Language: SystemVerilog - Size: 17.6 MB - Last synced at: about 19 hours ago - Pushed at: almost 2 years ago - Stars: 870 - Forks: 227

ultraembedded/cores

Various HDL (Verilog) IP Cores

Language: Verilog - Size: 211 KB - Last synced at: about 2 months ago - Pushed at: almost 4 years ago - Stars: 745 - Forks: 218

olofk/edalize

An abstraction library for interfacing EDA tools

Language: Python - Size: 1.07 MB - Last synced at: 5 days ago - Pushed at: 16 days ago - Stars: 681 - Forks: 200

dpretet/async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Language: Verilog - Size: 1.01 MB - Last synced at: about 17 hours ago - Pushed at: 12 months ago - Stars: 325 - Forks: 83

mshr-h/vscode-verilog-hdl-support

HDL support for VS Code

Language: TypeScript - Size: 2.23 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 318 - Forks: 83

tymonx/logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Language: SystemVerilog - Size: 820 KB - Last synced at: 9 days ago - Pushed at: over 5 years ago - Stars: 275 - Forks: 60

chipsalliance/Cores-VeeR-EL2

VeeR EL2 Core

Language: SystemVerilog - Size: 898 MB - Last synced at: 5 days ago - Pushed at: 6 days ago - Stars: 273 - Forks: 82

ZipCPU/sdspi

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

Language: Verilog - Size: 15.1 MB - Last synced at: about 17 hours ago - Pushed at: 4 months ago - Stars: 273 - Forks: 43

ZipCPU/wbuart32

A simple, basic, formally verified UART controller

Language: Verilog - Size: 1.19 MB - Last synced at: 9 months ago - Pushed at: about 1 year ago - Stars: 266 - Forks: 46

ZipCPU/dblclockfft

A configurable C++ generator of pipelined Verilog FFT cores

Language: C++ - Size: 1.08 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 204 - Forks: 28

ZipCPU/autofpga

A utility for Composing FPGA designs from Peripherals

Language: C++ - Size: 2.42 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 170 - Forks: 19

ZipCPU/vgasim

A Video display simulator

Language: Verilog - Size: 3.86 MB - Last synced at: about 17 hours ago - Pushed at: 9 months ago - Stars: 165 - Forks: 20

ZipCPU/openarty

An Open Source configuration of the Arty platform

Language: Verilog - Size: 14.2 MB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 122 - Forks: 24

ZipCPU/dpll

A collection of phase locked loop (PLL) related projects

Language: Verilog - Size: 690 KB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 99 - Forks: 26

ZipCPU/wbscope

A wishbone controlled scope for FPGA's

Language: Verilog - Size: 758 KB - Last synced at: about 17 hours ago - Pushed at: over 1 year ago - Stars: 80 - Forks: 6

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

Language: VHDL - Size: 1.91 GB - Last synced at: 2 days ago - Pushed at: 3 days ago - Stars: 77 - Forks: 0

dpretet/svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Language: Python - Size: 755 KB - Last synced at: 4 days ago - Pushed at: 6 months ago - Stars: 77 - Forks: 17

IBM/hdl-tools 📦

Facilitates building open source tools for working with hardware description languages (HDLs)

Language: Perl - Size: 40 KB - Last synced at: 4 months ago - Pushed at: over 5 years ago - Stars: 62 - Forks: 12

ZipCPU/interpolation

Digital Interpolation Techniques Applied to Digital Signal Processing

Language: Verilog - Size: 2.04 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 48 - Forks: 12

tymonx/virtio

Virtio implementation in SystemVerilog

Language: SystemVerilog - Size: 44.9 KB - Last synced at: 26 days ago - Pushed at: about 7 years ago - Stars: 47 - Forks: 11

ZipCPU/wbi2c

Wishbone controlled I2C controllers

Language: Verilog - Size: 759 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 44 - Forks: 10

ben-marshall/croyde-riscv

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

Language: SystemVerilog - Size: 754 KB - Last synced at: about 1 month ago - Pushed at: about 3 years ago - Stars: 44 - Forks: 7

sgherbst/svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

Language: SystemVerilog - Size: 253 KB - Last synced at: 4 days ago - Pushed at: over 4 years ago - Stars: 44 - Forks: 8

ethanuppal/marlin

🦀 No nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl

Language: Rust - Size: 2.54 MB - Last synced at: 14 days ago - Pushed at: 18 days ago - Stars: 41 - Forks: 3

microdynamics-cpu/tree-core-cpu

:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

Language: Scala - Size: 669 KB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 36 - Forks: 3

ZipCPU/zbasic

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

Language: Verilog - Size: 3.03 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 36 - Forks: 5

tscheipel/HaDes-V

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

Language: SystemVerilog - Size: 432 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 35 - Forks: 2

dbhi/vboard

Virtual development board for HDL design

Language: VHDL - Size: 383 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 33 - Forks: 5

ZipCPU/s6soc

CMod-S6 SoC

Language: Verilog - Size: 2.8 MB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 33 - Forks: 5

fredrequin/verilator_xilinx

Re-coded Xilinx primitives for Verilator use

Language: Verilog - Size: 151 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 30 - Forks: 2

FDUCSLG/ICS-2021Spring-FDU

Introduction to Computer Systems (II), Spring 2021

Language: C++ - Size: 24.8 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 30 - Forks: 17

vmunoz82/eda_tools

A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator.

Language: Dockerfile - Size: 17.6 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 24 - Forks: 4

ZipCPU/dbgbus

A collection of debugging busses developed and presented at zipcpu.com

Language: Verilog - Size: 324 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 23 - Forks: 3

Lampro-Mellon/Quasar

Quasar 2.0: Chisel equivalent of SweRV-EL2

Language: Scala - Size: 155 MB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 23 - Forks: 8

wyvernSemi/mem_model

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

Language: VHDL - Size: 2.71 MB - Last synced at: 23 days ago - Pushed at: 5 months ago - Stars: 22 - Forks: 3

kkiningh/rules_verilator

Bazel build rules for Verilator

Language: Starlark - Size: 37.1 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 20 - Forks: 14

nju-mips/noop-lo

A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.

Language: Verilog - Size: 19.4 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 19 - Forks: 5

scarv/scarv-cpu

SCARV: a side-channel hardened RISC-V platform

Language: Verilog - Size: 1.37 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 18 - Forks: 6

verilator/uvm Fork of chipsalliance/uvm-verilator

Universal Verification Methodology (UVM) base libraries, with edits for Verilator

Size: 0 Bytes - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 18 - Forks: 8

verilator/verilator_ext_tests

Extended and external tests for Verilator testing

Language: SystemVerilog - Size: 170 KB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 16 - Forks: 9

HEP-SoC/SoCMake

CMake based hardware build system

Language: CMake - Size: 6.01 MB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 16 - Forks: 2

ZipCPU/videozip

A ZipCPU SoC for the Nexys Video board supporting video functionality

Language: Verilog - Size: 9.34 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 16 - Forks: 1

poucotm/SublimeLinter-contrib-verilator

👌 This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)

Language: Python - Size: 88.9 KB - Last synced at: 12 days ago - Pushed at: 10 months ago - Stars: 16 - Forks: 6

ZipCPU/website

The ZipCPU blog

Language: HTML - Size: 187 MB - Last synced at: 25 days ago - Pushed at: 25 days ago - Stars: 15 - Forks: 8

tum-ei-eda/vrtlmod

vRTLmod modifies Verilator generated RTL simulation code for faul-injection purposes. It transforms source code with the help of LLVM/Clang-Tools and generates a fault injection API.

Language: C++ - Size: 601 KB - Last synced at: 10 days ago - Pushed at: 8 months ago - Stars: 13 - Forks: 5

wataru030-XIAOHEI/My-RISCV64-CORE-writing

一生一芯， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .

Language: C++ - Size: 1.2 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 13 - Forks: 3

MaxXSoft/Bossa

BOOM's Simulation Accelerator.

Language: Scala - Size: 104 KB - Last synced at: about 20 hours ago - Pushed at: over 3 years ago - Stars: 13 - Forks: 2

rodrigomelo9/verifying-foss-hdl-synthesizers

a project to check the FOSS synthesizers against vendors EDA tools

Language: Makefile - Size: 81.1 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 12 - Forks: 2

miree/gvi

GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.

Language: C++ - Size: 239 KB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 11 - Forks: 1

JasonBrave/pci-edu

SystemVerilog implemention of QEMU PCI edu device

Language: SystemVerilog - Size: 56.6 KB - Last synced at: 16 days ago - Pushed at: almost 2 years ago - Stars: 11 - Forks: 2

Risto97/systemc_uvm_verilator 📦

Language: C++ - Size: 1.42 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 11 - Forks: 0

arhamhashmi01/rv32i-pipeline-processor

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

Language: Verilog - Size: 357 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 10 - Forks: 0

esromneb/verilator-project-template

Template Verilator project for beginners

Language: C++ - Size: 59.6 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 10 - Forks: 1

xThaid/fpga-lb

A toy L4 load balancer running on FPGA

Language: C - Size: 832 KB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 10 - Forks: 0

semify-eda/go.debug

Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster

Language: SystemVerilog - Size: 11.9 MB - Last synced at: 9 days ago - Pushed at: over 3 years ago - Stars: 10 - Forks: 3

a2k-hanlon/linter-veriloghdl 📦

Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.

Language: CoffeeScript - Size: 784 KB - Last synced at: 11 months ago - Pushed at: almost 2 years ago - Stars: 9 - Forks: 2

fredrequin/verilator_gowin

Re-coded Gowin GW1N primitives for Verilator use

Language: Verilog - Size: 31.3 KB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 9 - Forks: 0

RISMicroDevices/RMR8PM3001A

Taurus 3001 RISC-V 64-bit Privileged Minimal System Processor for T110/T28 ASIC

Language: C++ - Size: 557 KB - Last synced at: 9 days ago - Pushed at: almost 3 years ago - Stars: 9 - Forks: 1

Rain92/vga_interface

Language: SystemVerilog - Size: 1.65 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 9 - Forks: 2

ShaheerSajid/RISCV

32-bit soft RISCV processor for FPGA applications

Language: C++ - Size: 13.3 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 0

SinaKarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

Language: VHDL - Size: 46.9 KB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 2

SymbiFlow/XilinxUnisimLibrary Fork of Xilinx/XilinxUnisimLibrary

Apache 2.0 licensed copy of the Xilinx Unisim library.

Language: Verilog - Size: 1.9 MB - Last synced at: about 1 year ago - Pushed at: almost 5 years ago - Stars: 8 - Forks: 1

ZipCPU/wbicapetwo

Wishbone to ICAPE interface conversion

Language: Verilog - Size: 177 KB - Last synced at: over 1 year ago - Pushed at: about 5 years ago - Stars: 7 - Forks: 1

Ray-Eldath/althas

A header-only C++ library that provides unit test facilities for Verilator which makes your testing procedure much easier.

Language: C++ - Size: 23.4 KB - Last synced at: 7 days ago - Pushed at: almost 5 years ago - Stars: 6 - Forks: 0

Risto97/pygears-uvm

SystemC UVM environment generator for PyGears components. RTL simulated with Verilator

Language: C++ - Size: 69.3 KB - Last synced at: 13 days ago - Pushed at: over 5 years ago - Stars: 6 - Forks: 3

esynr3z/playhdl

🪀 Tool to play with HDL (inspired by EdaPlayground)

Language: Python - Size: 27.3 KB - Last synced at: 9 months ago - Pushed at: over 2 years ago - Stars: 5 - Forks: 1

sfu-arch/muir-sim

muIR C++ Simulator

Language: C++ - Size: 434 MB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 5 - Forks: 3

weisrc/web-verilog-poc

Running verilog on hardware, desktop and the web

Language: C++ - Size: 167 KB - Last synced at: 16 days ago - Pushed at: about 3 years ago - Stars: 5 - Forks: 0

akashlevy/NEM-Relay-CGRA

Jade CGRA using NEM relay interconnect fabric. Related repositories: NEM-Relay-CGRA-Flow, NEM-Relay-CAD

Language: Verilog - Size: 1.74 GB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 5 - Forks: 3

memchk/cbench

A verilator testbench framework.

Language: C++ - Size: 11.7 KB - Last synced at: about 2 months ago - Pushed at: about 4 years ago - Stars: 4 - Forks: 0

jeudine/Mersenne-twister-hardware

A flexible hardware module written in SystemVerilog which implements the Mersene twister (using a 32-bit word length). A simulation and a test bench written in SystemC, which uses Verilator were created in order to verify the correctness and to measure performance of the hardware module.

Language: C++ - Size: 59.6 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 0

yangm2/verilator-example

Example of using various technologies together in a Verilator simulation

Language: Rust - Size: 42 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 3 - Forks: 1

yasnakateb/ChipyardIntegration

😱 RoCC Accelerator Integration with Chipyard

Size: 8.79 KB - Last synced at: 7 days ago - Pushed at: 6 months ago - Stars: 3 - Forks: 0

ArbnorSh/RV-PipelineCore

RISC-V processor in compliance with RV32IMZicsr

Language: Verilog - Size: 1.82 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 3 - Forks: 0

muhammadtalhasami/RV32I_Single_Cycle

This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.

Language: Verilog - Size: 168 KB - Last synced at: 2 months ago - Pushed at: 9 months ago - Stars: 3 - Forks: 0

ndyashas/Salaga-RV

Simple RISC-V CPUs running a baremental ray-tracer program.

Language: Verilog - Size: 884 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0

ECE320/riscv-tester

Tests your ECE 320 Single Cycle RISC-V Processor: Up to PD5

Language: Python - Size: 101 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0

gergoerdi/clash-bounce-bench

Benchmark for various methods of simulating Clash

Language: Haskell - Size: 69.3 KB - Last synced at: about 1 month ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 0

hsnaves/gigatron

Verilog model and simulator (emulator) for the Gigatron TTL microcomputer .

Language: C - Size: 43 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 3 - Forks: 1

kkiningh/rules_verilator_old 📦

A fork of Verilator that includes Bazel build rules

Language: C++ - Size: 6.6 MB - Last synced at: over 1 year ago - Pushed at: almost 6 years ago - Stars: 3 - Forks: 0

lbnlcomputerarch/vte

Verilator Testbench Environment

Language: C++ - Size: 131 KB - Last synced at: 6 months ago - Pushed at: about 6 years ago - Stars: 3 - Forks: 1

VisorFolks/cyanforge

An open source utility to build and simulate cores.

Language: Makefile - Size: 16.6 KB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 2 - Forks: 0

Flinner/PacmanFPGA

Classic Pacman Implementation on a Xilinx FPGA! Simulated with Verilator + SFML

Language: SystemVerilog - Size: 12.1 MB - Last synced at: 16 days ago - Pushed at: 5 months ago - Stars: 2 - Forks: 1

sifferman/fusesoc_project_template

A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.

Language: Makefile - Size: 4.88 KB - Last synced at: 4 days ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

fredrequin/verilator_helpers

C++ objects to help verilator simulations

Language: C - Size: 149 KB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 0

weisrc/nesv

NESystem Verilog

Language: SystemVerilog - Size: 1.11 MB - Last synced at: 13 days ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

DaulPavid/verilog_template

Boilerplate project template for verilog that includes directories for simulation, documentation, and formal verification.

Language: CMake - Size: 43 KB - Last synced at: about 2 months ago - Pushed at: almost 4 years ago - Stars: 2 - Forks: 0

DuinOS/AprendaFPGA

Algumas anotações de quem está aprendendo a sintetizar seu próprio microcontrolador em FPGA.

Size: 23.4 KB - Last synced at: 6 days ago - Pushed at: almost 4 years ago - Stars: 2 - Forks: 0

Rafa350/riscv

Experimental RISCV implementation

Language: SystemVerilog - Size: 798 KB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 2 - Forks: 0

VicoHBB/Verilator-SV-Template

This project template is designed to streamline the development of SystemVerilog projects using Verilator, GTKWave, and Make. The template includes a Makefile with various recipes for compiling, simulating, and visualizing the design. It also includes a directory structure for organizing the HDL files, test benches, and simulation waveforms.

Language: SystemVerilog - Size: 62.5 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0