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Topic: "verilator-testbench"

muhammadtalhasami/sv_verilator

System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool a c++ test bench. Verilator is basically a 2 state tool .

Language: C++ - Size: 16.6 MB - Last synced at: 2 months ago - Pushed at: 11 months ago - Stars: 4 - Forks: 1

CT7-labs/argon-cpu

16-bit CPU written in Verilog

Language: Verilog - Size: 128 KB - Last synced at: 20 days ago - Pushed at: 20 days ago - Stars: 0 - Forks: 0

calvera/alarm-clock

simple alarm clock in FPGA

Language: Verilog - Size: 50.8 KB - Last synced at: 30 days ago - Pushed at: 30 days ago - Stars: 0 - Forks: 0

Abdelrahman1810/ALU-testbench-verilator

This repository provides a Verilator-based testbench for an ALU (Arithmetic Logic Unit), using VPW library (Verilator Python Wrapper). It includes a Python testbench that verifies various ALU operations.

Language: Python - Size: 10 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

Related Topics
systemverilog 3 verilog 2 verilator 2 system-verilog-testbench 1 testbench 1 verification 1 verilator- 1 verilog-hdl 1 python 1 vpw 1 alarm-clock 1 fpga 1 cpu 1 cpu-simulator 1 homebrew-computer 1