VUnit/vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

Language: VHDL - Size: 14 MB - Last synced at: 5 days ago - Pushed at: 6 days ago - Stars: 784 - Forks: 279

ultraembedded/cores

Various HDL (Verilog) IP Cores

Language: Verilog - Size: 211 KB - Last synced at: 6 months ago - Pushed at: about 4 years ago - Stars: 745 - Forks: 218

PyHDI/Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

Language: Python - Size: 701 KB - Last synced at: about 1 month ago - Pushed at: about 1 year ago - Stars: 724 - Forks: 199

NNgen/nngen

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

Language: Python - Size: 1.41 MB - Last synced at: 17 days ago - Pushed at: almost 2 years ago - Stars: 354 - Forks: 47

dpretet/async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Language: Verilog - Size: 1.01 MB - Last synced at: 2 months ago - Pushed at: over 1 year ago - Stars: 349 - Forks: 83

mshr-h/vscode-verilog-hdl-support

HDL support for VS Code

Language: TypeScript - Size: 2.27 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 333 - Forks: 82

PyHDI/veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

Language: Python - Size: 11.4 MB - Last synced at: about 1 month ago - Pushed at: about 1 year ago - Stars: 320 - Forks: 58

ultraembedded/core_jpeg

High throughput JPEG decoder in Verilog for FPGA

Language: Verilog - Size: 171 KB - Last synced at: 6 months ago - Pushed at: over 3 years ago - Stars: 221 - Forks: 43

Gowtham1729/Image-Processing

Image Processing Toolbox in Verilog using Basys3 FPGA

Language: VHDL - Size: 25 MB - Last synced at: 6 days ago - Pushed at: 3 months ago - Stars: 212 - Forks: 40

AUCOHL/Fault

A complete open-source design-for-testing (DFT) Solution

Language: Swift - Size: 4.3 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 153 - Forks: 32

snbk001/Verilog-Design-Examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier

Language: Verilog - Size: 126 KB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 132 - Forks: 23

ben-marshall/uart

A simple implementation of a UART modem in Verilog.

Language: Verilog - Size: 53.7 KB - Last synced at: 5 months ago - Pushed at: almost 4 years ago - Stars: 123 - Forks: 22

michaelehab/AES-Verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

Language: Verilog - Size: 8.73 MB - Last synced at: 16 days ago - Pushed at: about 3 years ago - Stars: 105 - Forks: 26

thedatabusdotio/fpga-ml-accelerator

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

Language: Verilog - Size: 21.5 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 103 - Forks: 23

gupta409/Processor-UVM-Verification

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

Language: Verilog - Size: 355 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 95 - Forks: 33

Michaelvll/RISCV_CPU

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

Language: C - Size: 23.5 MB - Last synced at: 22 days ago - Pushed at: over 5 years ago - Stars: 86 - Forks: 14

bojackchen/digital-flow

This is a tutorial on standard digital design flow

Language: Tcl - Size: 710 KB - Last synced at: about 1 month ago - Pushed at: about 4 years ago - Stars: 78 - Forks: 30

aptx1231/BUAA_CO

2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)

Language: Verilog - Size: 25.1 MB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 72 - Forks: 18

metr0jw/Spiking-Neural-Network-on-FPGA

Leaky Integrate and Fire (LIF) model implementation for FPGA

Language: Verilog - Size: 157 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 71 - Forks: 6

neelkshah/MIPS-Processor

5-stage pipelined 32-bit MIPS microprocessor in Verilog

Language: Verilog - Size: 138 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 64 - Forks: 13

mongrelgem/Verilog-Adders

Implementing Different Adder Structures in Verilog

Language: Verilog - Size: 77.1 KB - Last synced at: 7 months ago - Pushed at: almost 6 years ago - Stars: 60 - Forks: 16

RuSys/Verugent

Verilog generation tool written in Rust

Language: Rust - Size: 77.1 KB - Last synced at: 1 day ago - Pushed at: about 2 years ago - Stars: 59 - Forks: 5

TheSUPERCD/8bit_MicroComputer_Verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

Language: Verilog - Size: 173 KB - Last synced at: 4 months ago - Pushed at: over 2 years ago - Stars: 54 - Forks: 15

Weiyet/RTLStructLib

RTL data structure

Language: SystemVerilog - Size: 564 KB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 52 - Forks: 4

defparam/higan-verilog

This is a higan/Verilator co-simulation example/framework

Language: C++ - Size: 1.36 MB - Last synced at: 4 months ago - Pushed at: over 7 years ago - Stars: 50 - Forks: 7

Jed-Z/computer-organization-lab

中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU

Language: Verilog - Size: 13.8 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 45 - Forks: 22

maxs-well/Ethernet-design-verilog

Gigabit Ethernet UDP communication driver

Language: Verilog - Size: 30.3 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 43 - Forks: 34

jfoshea/Viterbi-Decoder-in-Verilog

An efficient implementation of the Viterbi decoding algorithm in Verilog

Language: Verilog - Size: 7.57 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 41 - Forks: 20

ashishrana160796/verilog-starter-tutorials 📦

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

Language: Verilog - Size: 25.4 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 34 - Forks: 17

tomtor/HDL-deflate

FPGA implementation of deflate (de)compress RFC 1950/1951

Language: Verilog - Size: 476 KB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 34 - Forks: 1

lightcode/8bit-computer

Simple 8-bit computer build in Verilog

Language: Verilog - Size: 76.2 KB - Last synced at: over 2 years ago - Pushed at: almost 8 years ago - Stars: 31 - Forks: 4

Arjun-Narula/Traffic-Light-Controller-using-Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

Language: JavaScript - Size: 2.07 MB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 29 - Forks: 7

maazm007/vsdsquadron-mini-internship

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

Language: C - Size: 102 MB - Last synced at: 28 days ago - Pushed at: 28 days ago - Stars: 28 - Forks: 15

geraked/verilog-rle

Verilog Implementation of Run Length Encoding for RGB Image Compression

Language: Verilog - Size: 11.6 MB - Last synced at: 3 months ago - Pushed at: about 4 years ago - Stars: 25 - Forks: 4

chili-chips-ba/openXC7-TetriSaraj

Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.

Language: Verilog - Size: 25.1 MB - Last synced at: 5 months ago - Pushed at: 6 months ago - Stars: 24 - Forks: 1

maxs-well/ad7606-driver-verilog

AD7606 driver verilog

Language: Verilog - Size: 3.88 MB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 23 - Forks: 8

AISeQLab/Level_0_KV260_FPGA

A sample FPGA project on KV260

Language: C - Size: 74.4 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 22 - Forks: 4

spider-tronix/VLSI 📦

RISC V core implementation using Verilog.

Language: Verilog - Size: 1.53 MB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 22 - Forks: 4

Wissance/QuickSPI

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

Language: Verilog - Size: 127 KB - Last synced at: 5 months ago - Pushed at: over 7 years ago - Stars: 22 - Forks: 7

mihir8181/VerilogHDL-Codes

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

Language: Verilog - Size: 3.45 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 21 - Forks: 3

sarthak268/Embedded_Logic_and_Design

This repository contains all labs done as a part of the Embedded Logic and Design course.

Size: 14.7 MB - Last synced at: over 1 year ago - Pushed at: about 7 years ago - Stars: 21 - Forks: 2

sdasgup3/parallel-processor-design

Super scalar Processor design

Language: Verilog - Size: 137 KB - Last synced at: 4 months ago - Pushed at: almost 11 years ago - Stars: 21 - Forks: 3

cvonk/FPGA_SPI

Connecting FPGA and Arduino using SPI.

Language: Verilog - Size: 2.52 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 20 - Forks: 3

yasnakateb/PipelinedARM

💎 A 32-bit ARM Processor Implementation in Verilog HDL

Language: Verilog - Size: 55.7 KB - Last synced at: 5 months ago - Pushed at: over 3 years ago - Stars: 19 - Forks: 3

JN513/Risco-5

Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.

Language: Verilog - Size: 3.49 MB - Last synced at: 2 months ago - Pushed at: 10 months ago - Stars: 18 - Forks: 1

aklsh/getting-started-with-verilog

Verilog modules for beginners

Language: Verilog - Size: 44.9 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 18 - Forks: 9

splAcharya/DigitalOscilloscope_Zynq7000Soc

A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.

Size: 71.2 MB - Last synced at: 9 months ago - Pushed at: about 5 years ago - Stars: 18 - Forks: 4

b1f6c1c4/Deep-DarkFantasy

Global Dark Mode for ALL apps on ANY platforms.

Language: Verilog - Size: 3.95 MB - Last synced at: 5 months ago - Pushed at: almost 2 years ago - Stars: 17 - Forks: 0

jge162/verilog_compiler

Verilog_Compiler is now available in GitHub Marketplace! This tool can quickly compile Verilog code and check for errors, making it an essential tool for developers.

Language: Verilog - Size: 520 KB - Last synced at: 6 days ago - Pushed at: 10 months ago - Stars: 15 - Forks: 0

BrianHGinc/Verilog-Floating-Point-Clock-Divider

Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.

Language: Verilog - Size: 289 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 14 - Forks: 1

Technocrats-nitw/HacktoberFest

This Repository invites freelancer friendly neighbourhood developers to contribute to open source .

Language: Jupyter Notebook - Size: 21.9 MB - Last synced at: 4 months ago - Pushed at: almost 3 years ago - Stars: 14 - Forks: 70

maxs-well/LMS-sound-filtering-by-Verilog

LMS sound filtering by Verilog

Language: Verilog - Size: 10.3 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 14 - Forks: 5

cla7aye15I4nd/trivial-riscv-cpu

A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz.

Language: Verilog - Size: 4.85 MB - Last synced at: 5 months ago - Pushed at: over 5 years ago - Stars: 14 - Forks: 1

cspang1/jcap

JAMMA Custom Arcade Project

Language: Propeller Spin - Size: 98 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 13 - Forks: 3

icglue/icglue

A Tcl-Library for scripted HDL generation

Language: Tcl - Size: 1.6 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 12 - Forks: 2

Eyantra698Sumanto/Spice-to-Verilog-Converter

Spice to Verilog Converter

Language: Python - Size: 23.4 KB - Last synced at: 4 months ago - Pushed at: about 2 years ago - Stars: 12 - Forks: 1

yasnakateb/NoCRouter

🎞️ NoC router in Verilog with FIFO

Language: Verilog - Size: 269 KB - Last synced at: about 1 month ago - Pushed at: almost 3 years ago - Stars: 12 - Forks: 2

MatejGomboc/Verilog-I2S-Transciever

I2S transciever implemented in Verilog HDL

Language: Verilog - Size: 77.1 KB - Last synced at: over 2 years ago - Pushed at: almost 8 years ago - Stars: 12 - Forks: 7

LSC-Unicamp/processor_ci

Utility scripts to configure processors, perform synthesis, load onto FPGAs, and other tasks related to ProcessorCI.

Language: SystemVerilog - Size: 1.53 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 11 - Forks: 1

nishit0072e/RTL-to-GDSII

Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout generation

Language: C++ - Size: 7.92 MB - Last synced at: 28 days ago - Pushed at: 28 days ago - Stars: 11 - Forks: 2

djzenma/RV32IC-CPU

Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.

Language: Verilog - Size: 3.19 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 11 - Forks: 2

powerplayer9/Voice-Based-Motor-Control

A verilog HDL based project to control a servomotor with voice commands from an android phone.

Language: Verilog - Size: 547 KB - Last synced at: about 1 year ago - Pushed at: almost 6 years ago - Stars: 11 - Forks: 2

mshr-h/motion_estimation_processor_fullsearch

Fullsearch based Motion Estimation Processor written in Verilog-HDL

Language: Verilog - Size: 1.7 MB - Last synced at: 5 months ago - Pushed at: over 8 years ago - Stars: 11 - Forks: 3

Nidhinchandran47/my_rtl_code

Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog

Language: Verilog - Size: 1.67 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 10 - Forks: 1

gojimmypi/ulx3s-examples

Collection of various ulx3s examples

Language: Python - Size: 16.1 MB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 10 - Forks: 8

yasnakateb/PipelinedMIPS

🔮 A 16-bit MIPS Processor Implementation in Verilog HDL

Language: Verilog - Size: 75.2 KB - Last synced at: 2 months ago - Pushed at: almost 5 years ago - Stars: 10 - Forks: 0

tharunchitipolu/RISC-V-32I-based-core-with-Advanced-Extensible-Interface

5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.

Language: Verilog - Size: 518 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 9 - Forks: 0

jg-fossh/Goldschmidt_Integer_Divider_Parallel

A Goldschmidt integer divider written in verilog. Similar to Newton-Raphson but the divison step can be pipelined.

Language: Verilog - Size: 82.4 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 9 - Forks: 2

ekb0412/100DaysofRTL

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

Language: Verilog - Size: 12 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 9 - Forks: 1

sbaldzenka/TangNano4k_examples

Examples for Gowin Tang Nano 4k FPGA-board.

Language: C - Size: 1.13 MB - Last synced at: 6 months ago - Pushed at: about 3 years ago - Stars: 9 - Forks: 4

Teddy-van-Jerry/ARM_Lite

A lite version of ARM CPU that extends ARM LEGv8

Language: Verilog - Size: 2.83 MB - Last synced at: 5 months ago - Pushed at: over 3 years ago - Stars: 9 - Forks: 1

KevinHexin/FPGA-Bicubic-interpolation

use Verilog HDL implemente bicubic interpolation in FPGA

Language: Coq - Size: 2.07 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 9 - Forks: 3

michg/riscv32_beluga

c compiler beluga with riscv32 backend

Language: C - Size: 2.81 MB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 9 - Forks: 0

melzareix/mips-pipeline

Mips Pipeline Processor

Language: Verilog - Size: 36.1 KB - Last synced at: over 2 years ago - Pushed at: almost 7 years ago - Stars: 9 - Forks: 2

luk3Sky/Building-A-Processor---Project

Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic

Language: Verilog - Size: 880 KB - Last synced at: 5 months ago - Pushed at: over 6 years ago - Stars: 8 - Forks: 1

pendkeomkar/SPI

Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI bus provides a synchronized serial link with performance in MHz range.The project implements the bridge between the two protocols and serves as an interface between these two which allow direct communication and a solution to reduce development time and cost for complex embedded systems.

Size: 8.96 MB - Last synced at: over 2 years ago - Pushed at: almost 7 years ago - Stars: 8 - Forks: 2

JN513/Grande-Risco-5

Grande RISCO 5 is a RISC-V RV32IMBC_Zicsr processor with a 5-stage pipeline, developed in just a few days off.

Language: Verilog - Size: 1.15 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 7 - Forks: 0

Choaib-ELMADI/getting-started-with-verilog

Getting started with Verilog: Hardware Description Language for digital design.

Language: Verilog - Size: 9.87 MB - Last synced at: 21 days ago - Pushed at: 6 months ago - Stars: 7 - Forks: 0

samiyaalizaidi/Equalizer

Fixed Point FPGA-based Hardware Implementation of a 32-tap Low Pass FIR Filter for Audio Applications

Language: Verilog - Size: 536 KB - Last synced at: about 2 months ago - Pushed at: 8 months ago - Stars: 7 - Forks: 1

JN513/Pequeno-Risco-5

Processador RISC-V de ciclo único com implementação RV32I construído em alguns dias de folga.

Language: Verilog - Size: 340 KB - Last synced at: 9 days ago - Pushed at: over 1 year ago - Stars: 7 - Forks: 0

maazm007/100Daysof_RTL

The Repository contains the code of various Digital Circuits

Language: Verilog - Size: 20.6 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 7 - Forks: 1

tharunchitipolu/Multi-operations-toolbox-with-baugh-wooley-multiplier

Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier

Language: Verilog - Size: 52.7 KB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 7 - Forks: 1

AbdullahAnsarii/BandPassFilter

FIR band-pass filter using Verilog HDL.

Language: Verilog - Size: 1.6 MB - Last synced at: almost 2 years ago - Pushed at: almost 5 years ago - Stars: 7 - Forks: 3

maxs-well/BPSK_verilog

BPSK verilog implemention

Language: Verilog - Size: 63.5 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 7 - Forks: 2

addisonElliott/LogiFindFPGATest

This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.

Language: Verilog - Size: 1.7 MB - Last synced at: 5 months ago - Pushed at: almost 6 years ago - Stars: 7 - Forks: 3

Mozes-Y/HDLBits_Solutions

My HDLBits solutions.

Language: Verilog - Size: 57.6 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 6 - Forks: 1

cnily03-hive/single-cycle-cpu

Single-Cycle CPU for Homework of Computer System Design in CUMT

Language: Verilog - Size: 900 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 6 - Forks: 0

ErickMaRi/HDL-Bitnet-1.58

Transformer Bitnet en Verilog

Language: Verilog - Size: 4 MB - Last synced at: about 13 hours ago - Pushed at: about 1 year ago - Stars: 6 - Forks: 1

Multimedia-Processing/Digital-Logic-Design

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

Language: Verilog - Size: 181 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 6 - Forks: 2

vSasakiv/RV32I_Processor

Risc-V 32i processor written in the Verilog HDL

Language: Verilog - Size: 6.61 MB - Last synced at: 10 months ago - Pushed at: over 2 years ago - Stars: 6 - Forks: 0

MalakSadek/StaticTimingAnalyzer

A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)

Language: HTML - Size: 1.2 MB - Last synced at: 4 months ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 3

pandyah5/ECE241_Verilog

This repo contains all the Verilog HDL files that I made during the course.

Language: Verilog - Size: 361 KB - Last synced at: 6 days ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 0

Sanskar777/Dynamic-branch-predictor-in-pipelined-processors

Language: Verilog - Size: 253 KB - Last synced at: 6 months ago - Pushed at: over 5 years ago - Stars: 6 - Forks: 1

pvgupta24/Von-Neumann-Architecture-CPU

Implementation of 8-Bit CPU based on Von-Neumann Architechture in HDL

Language: Verilog - Size: 204 KB - Last synced at: 28 days ago - Pushed at: almost 8 years ago - Stars: 6 - Forks: 1

IzyaSoft/EasyHDLLib

A coocbook of HDL (primarily Verilog) modules

Language: Verilog - Size: 315 KB - Last synced at: 4 months ago - Pushed at: over 8 years ago - Stars: 6 - Forks: 0

RISC-KC/basic_rv32s

🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.

Language: Verilog - Size: 78.2 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 5 - Forks: 0

NellyW8/VeriReason

This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

Language: Python - Size: 272 KB - Last synced at: about 2 months ago - Pushed at: 2 months ago - Stars: 5 - Forks: 1

MohamedHussein27/SPI_Slave_With_Single_Port_Memory

This repository contains the implementation of an SPI (Serial Peripheral Interface) communication protocol with sigle port sync RAM. The project includes the design and code for an SPI Slave, a single-port asynchronous RAM, and an SPI Wrapper that connects the RAM and SPI Slave.

Language: Verilog - Size: 2.18 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 5 - Forks: 0

daringpatil3134/SPI_Serial_Peripheral_Interface_Verilog_Modules

Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device

Language: Verilog - Size: 29.3 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 5 - Forks: 2

yigitbektasgursoy/Motion_Estimation_Hardware_Verilog

Motion Estimation implementation by using Verilog HDL

Language: Verilog - Size: 2.85 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 5 - Forks: 0